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[PATCH v3 09/27] mtd: nand: omap2: manage NAND interrupts

From Roger Quadros <rogerq@ti.com>
Newsgroups linux.kernel
Subject [PATCH v3 09/27] mtd: nand: omap2: manage NAND interrupts
Date 2015-09-18 17:20 +0200
Message-ID <qa5Ca-6mB-5@gated-at.bofh.it> (permalink)
References <qa5iO-5JO-13@gated-at.bofh.it>
Organization linux.* mail to news gateway

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Manage NAND interrupts here using the GPMC IRQ ops.

This causes performance in prefetch-irq mode to be increased

from
[   38.252811] mtd_speedtest: eraseblock write speed is 5576 KiB/s
[   39.265259] mtd_speedtest: eraseblock read speed is 8192 KiB/s

to
[   35.666446] mtd_speedtest: eraseblock write speed is 6537 KiB/s
[   36.444842] mtd_speedtest: eraseblock read speed is 10680 KiB/s

Test results on dra7-evm using mtd_speedtest.ko

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 drivers/mtd/nand/omap2.c | 65 +++++++++++++++++++++++-------------------------
 1 file changed, 31 insertions(+), 34 deletions(-)

diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 0eb0b8c..267bcdd 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -162,8 +162,7 @@ struct omap_nand_info {
 	enum omap_ecc			ecc_opt;
 	struct completion		comp;
 	struct dma_chan			*dma;
-	int				gpmc_irq_fifo;
-	int				gpmc_irq_count;
+	int				gpmc_irq;
 	enum {
 		OMAP_NAND_IO_READ = 0,	/* read */
 		OMAP_NAND_IO_WRITE,	/* write */
@@ -579,12 +578,17 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 {
 	struct omap_nand_info *info = (struct omap_nand_info *) dev;
 	u32 bytes;
+	u32 irqstatus;
+
+	irqstatus = info->ops->nand_irq_status();
+	if (!irqstatus)
+		return IRQ_NONE;
 
 	bytes = readl(info->reg.gpmc_prefetch_status);
 	bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
 	bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
 	if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
-		if (this_irq == info->gpmc_irq_count)
+		if (irqstatus & GPMC_IRQENABLE_TERMCOUNT)
 			goto done;
 
 		if (info->buf_len && (info->buf_len < bytes))
@@ -601,17 +605,25 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 						(u32 *)info->buf, bytes >> 2);
 		info->buf = info->buf + bytes;
 
-		if (this_irq == info->gpmc_irq_count)
+		if (irqstatus & GPMC_IRQENABLE_TERMCOUNT)
 			goto done;
 	}
 
+	/* Clear FIFOEVENT STATUS */
+	info->ops->nand_irq_clear(GPMC_NAND_IRQ_FIFOEVENT);
+
 	return IRQ_HANDLED;
 
 done:
 	complete(&info->comp);
 
-	disable_irq_nosync(info->gpmc_irq_fifo);
-	disable_irq_nosync(info->gpmc_irq_count);
+	/* Clear FIFOEVENT and TERMCOUNT STATUS */
+	info->ops->nand_irq_clear(GPMC_NAND_IRQ_FIFOEVENT);
+	info->ops->nand_irq_clear(GPMC_NAND_IRQ_TERMCOUNT);
+
+	/* Disable Interrupt generation */
+	info->ops->nand_irq_disable(GPMC_NAND_IRQ_FIFOEVENT);
+	info->ops->nand_irq_disable(GPMC_NAND_IRQ_TERMCOUNT);
 
 	return IRQ_HANDLED;
 }
@@ -646,8 +658,9 @@ static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
 
 	info->buf_len = len;
 
-	enable_irq(info->gpmc_irq_count);
-	enable_irq(info->gpmc_irq_fifo);
+	/* Enable Interrupt generation */
+	info->ops->nand_irq_enable(GPMC_NAND_IRQ_TERMCOUNT);
+	info->ops->nand_irq_enable(GPMC_NAND_IRQ_FIFOEVENT);
 
 	/* waiting for read to complete */
 	wait_for_completion(&info->comp);
@@ -696,8 +709,9 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd,
 
 	info->buf_len = len;
 
-	enable_irq(info->gpmc_irq_count);
-	enable_irq(info->gpmc_irq_fifo);
+	/* Enable Interrupt generation */
+	info->ops->nand_irq_enable(GPMC_NAND_IRQ_TERMCOUNT);
+	info->ops->nand_irq_enable(GPMC_NAND_IRQ_FIFOEVENT);
 
 	/* waiting for write to complete */
 	wait_for_completion(&info->comp);
@@ -1776,35 +1790,18 @@ static int omap_nand_probe(struct platform_device *pdev)
 		break;
 
 	case NAND_OMAP_PREFETCH_IRQ:
-		info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
-		if (info->gpmc_irq_fifo <= 0) {
-			dev_err(&pdev->dev, "error getting fifo irq\n");
-			err = -ENODEV;
-			goto return_error;
-		}
-		err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
-					omap_nand_irq, IRQF_SHARED,
-					"gpmc-nand-fifo", info);
-		if (err) {
-			dev_err(&pdev->dev, "requesting irq(%d) error:%d",
-						info->gpmc_irq_fifo, err);
-			info->gpmc_irq_fifo = 0;
-			goto return_error;
-		}
-
-		info->gpmc_irq_count = platform_get_irq(pdev, 1);
-		if (info->gpmc_irq_count <= 0) {
-			dev_err(&pdev->dev, "error getting count irq\n");
+		info->gpmc_irq = platform_get_irq(pdev, 0);
+		if (info->gpmc_irq <= 0) {
+			dev_err(&pdev->dev, "error getting GPMC irq\n");
 			err = -ENODEV;
 			goto return_error;
 		}
-		err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
-					omap_nand_irq, IRQF_SHARED,
-					"gpmc-nand-count", info);
+		err = devm_request_irq(&pdev->dev, info->gpmc_irq,
+				       omap_nand_irq, IRQF_SHARED,
+				       DRIVER_NAME, info);
 		if (err) {
 			dev_err(&pdev->dev, "requesting irq(%d) error:%d",
-						info->gpmc_irq_count, err);
-			info->gpmc_irq_count = 0;
+						info->gpmc_irq, err);
 			goto return_error;
 		}
 
-- 
2.1.4

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Thread

[PATCH v3 00/27] memory: omap-gpmc: mtd: nand: Support GPMC NAND on non-OMAP platforms Roger Quadros <rogerq@ti.com> - 2015-09-18 17:00 +0200
  [PATCH v3 25/27] ARM: dts: am335x: Provide NAND ready pin Roger Quadros <rogerq@ti.com> - 2015-09-18 17:00 +0200
  [PATCH v3 15/27] memory: omap-gpmc: Support general purpose input for WAITPINs Roger Quadros <rogerq@ti.com> - 2015-09-18 17:00 +0200
  [PATCH v3 26/27] ARM: dts: dm816x: Fix gpmc and NAND node Roger Quadros <rogerq@ti.com> - 2015-09-18 17:00 +0200
  [PATCH v3 22/27] ARM: dts: am437x: Fix NAND device nodes Roger Quadros <rogerq@ti.com> - 2015-09-18 17:00 +0200
  [PATCH v3 10/27] mtd: nand: omap: Copy platform data parameters to omap_nand_info data Roger Quadros <rogerq@ti.com> - 2015-09-18 17:00 +0200
  [PATCH v3 20/27] ARM: dts: dra7: Fix NAND device nodes. Roger Quadros <rogerq@ti.com> - 2015-09-18 17:00 +0200
  [PATCH v3 19/27] memory: omap-gpmc: Prevent GPMC_STATUS from being accessed via gpmc_regs Roger Quadros <rogerq@ti.com> - 2015-09-18 17:00 +0200
  [PATCH v3 13/27] memory: omap-gpmc: Prevent mapping into 1st 16MB Roger Quadros <rogerq@ti.com> - 2015-09-18 17:00 +0200
  [PATCH v3 18/27] mtd: nand: omap2: Implement NAND ready using gpiolib Roger Quadros <rogerq@ti.com> - 2015-09-18 17:00 +0200
  [PATCH v3 21/27] ARM: dts: dra7x-evm: Provide NAND ready pin Roger Quadros <rogerq@ti.com> - 2015-09-18 17:00 +0200
  [PATCH v3 11/27] mtd: nand: omap: Clean up device tree support Roger Quadros <rogerq@ti.com> - 2015-09-18 17:00 +0200
  [PATCH v3 05/27] memory: omap-gpmc: Add GPMC-NAND ops to get writebufferempty status Roger Quadros <rogerq@ti.com> - 2015-09-18 17:00 +0200
  [PATCH v3 27/27] ARM: dts: omap3: Fix gpmc and NAND nodes Roger Quadros <rogerq@ti.com> - 2015-09-18 17:00 +0200
  [PATCH v3 14/27] memory: omap-gpmc: Move device tree binding to correct location Roger Quadros <rogerq@ti.com> - 2015-09-18 17:10 +0200
  [PATCH v3 17/27] memory: omap-gpmc: Add irqchip support to the gpiochip Roger Quadros <rogerq@ti.com> - 2015-09-18 17:10 +0200
  [PATCH v3 09/27] mtd: nand: omap2: manage NAND interrupts Roger Quadros <rogerq@ti.com> - 2015-09-18 17:20 +0200
  [PATCH v3 12/27] mtd: nand: omap: Update DT binding documentation Roger Quadros <rogerq@ti.com> - 2015-09-18 17:20 +0200
  [PATCH v3 07/27] memory: omap-gpmc: Remove NAND IRQ code Roger Quadros <rogerq@ti.com> - 2015-09-18 17:20 +0200
  [PATCH v3 16/27] memory: omap-gpmc: Reserve WAITPIN if needed for WAIT monitoring Roger Quadros <rogerq@ti.com> - 2015-09-18 17:20 +0200
  [PATCH v3 04/27] mtd: nand: omap2: Use gpmc_omap_get_nand_ops() to get NAND registers Roger Quadros <rogerq@ti.com> - 2015-09-18 17:30 +0200
  [PATCH v3 08/27] memory: omap-gpmc: Add IRQ ops for GPMC-NAND interface Roger Quadros <rogerq@ti.com> - 2015-09-18 17:30 +0200
  [PATCH v3 02/27] ARM: OMAP2+: gpmc: Add gpmc timings and settings to platform data Roger Quadros <rogerq@ti.com> - 2015-09-18 17:30 +0200
  [PATCH v3 01/27] ARM: OMAP2+: gpmc: Add platform data Roger Quadros <rogerq@ti.com> - 2015-09-18 17:30 +0200
  [PATCH v3 03/27] memory: omap-gpmc: Introduce GPMC to NAND interface Roger Quadros <rogerq@ti.com> - 2015-09-18 17:30 +0200
  [PATCH v3 06/27] mtd: nand: omap2: Switch to using GPMC-NAND ops for writebuffer empty check Roger Quadros <rogerq@ti.com> - 2015-09-18 17:30 +0200

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