Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1563328 > unrolled thread

[PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support to Exynos5433

Back to article view | Back to linux.kernel

This discussion starts older than the indexed window; earlier articles aren't shown. The article labeled Started by below is the oldest one visible, not the original post.

Contents

  [PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support to  Exynos5433 Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
    [PATCH 1/7] drm/exynos/hdmi: add 297MHz pixel clock support Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
    [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
      Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd  fields Ville Syrjälä <ville.syrjala@linux.intel.com> - 2017-01-20 15:00 +0100
        Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda <a.hajda@samsung.com> - 2017-01-23 10:20 +0100
          Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd  fields Ville Syrjälä <ville.syrjala@linux.intel.com> - 2017-01-25 15:10 +0100
            Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda <a.hajda@samsung.com> - 2017-01-26 09:30 +0100
              Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd  fields Ville Syrjälä <ville.syrjala@linux.intel.com> - 2017-01-26 11:50 +0100
    [PATCH 3/7] drm/exynos/hdmi: fix PLL for 27MHz settings Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
    [PATCH 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD  modes Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
      Re: [PATCH 7/7] arm64: dts: exynos: configure TV path clocks for  Ultra HD modes Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-20 16:00 +0100
        [PATCH v2 7/7] arm64: dts: exynos: configure TV path clocks for Ultra  HD modes Andrzej Hajda <a.hajda@samsung.com> - 2017-01-23 09:00 +0100
          Re: [PATCH v2 7/7] arm64: dts: exynos: configure TV path clocks for  Ultra HD modes Marek Szyprowski <m.szyprowski@samsung.com> - 2017-01-23 10:10 +0100
            [PATCH v3 7/7] arm64: dts: exynos: configure TV path clocks for Ultra  HD modes Andrzej Hajda <a.hajda@samsung.com> - 2017-01-23 11:10 +0100
              Re: [PATCH v3 7/7] arm64: dts: exynos: configure TV path clocks for  Ultra HD modes Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-23 17:40 +0100
    Re: [PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support  to Exynos5433 Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-20 15:50 +0100

#1563328 — [PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support to Exynos5433

Hi Inki,

This patchset adds support for UltraHD and intrelace modes on DECON and HDMI
drivers of Exynos5433 chipset. To fully support it on TM2(e) platforms MHL
patches are alse required which will be posted in separate patchset.

Krzysztof, DTS patch do not depend on the previous patches, so there is
no need to synchronize branches.

Regards
Andrzej


Andrzej Hajda (7):
  drm/exynos/hdmi: add 297MHz pixel clock support
  drm/exynos/hdmi: fix VSI infoframe registers
  drm/exynos/hdmi: fix PLL for 27MHz settings
  drm/exynos/hdmi: add bridge support
  drm/exynos/decon5433: add support for interlace modes
  drm/exynos/decon5433: signal vblank only on odd fields
  arm64: dts: exynos: configure TV path clocks for Ultra HD modes

 arch/arm64/boot/dts/exynos/exynos5433.dtsi    |  3 +
 drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 52 ++++++++++++-----
 drivers/gpu/drm/exynos/exynos_hdmi.c          | 80 +++++++++++++++++++++------
 include/video/exynos5433_decon.h              |  2 +
 4 files changed, 107 insertions(+), 30 deletions(-)

-- 
2.7.4

[toc] | [next] | [standalone]

#1563329 — [PATCH 1/7] drm/exynos/hdmi: add 297MHz pixel clock support

297MHz is used by Ultra HD modes.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
---
 drivers/gpu/drm/exynos/exynos_hdmi.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 5ed8b1e..bef8965 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -587,6 +587,15 @@ static const struct hdmiphy_config hdmiphy_5433_configs[] = {
 			0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40,
 		},
 	},
+	{
+		.pixel_clock = 297000000,
+		.conf = {
+			0x01, 0x51, 0x3E, 0x05, 0x40, 0xF0, 0x88, 0xC2,
+			0x52, 0x53, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
+			0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
+			0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
+		},
+	},
 };
 
 static const char * const hdmi_clk_gates4[] = {
-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1563330 — [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields

In case of interlace mode irq is generated for odd and even fields, but
vblank should be signaled only for the last emitted field.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
---
 drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 7 +++++++
 include/video/exynos5433_decon.h              | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 46434ba9..ad8b93a 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -591,6 +591,13 @@ static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 
 	if (val) {
 		writel(val, ctx->addr + DECON_VIDINTCON1);
+		if (ctx->out_type & IFTYPE_HDMI) {
+			val = readl(ctx->addr + DECON_VIDOUTCON0);
+			val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
+			if (val ==
+			    (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
+				return IRQ_HANDLED;
+		}
 		drm_crtc_handle_vblank(&ctx->crtc->base);
 	}
 
diff --git a/include/video/exynos5433_decon.h b/include/video/exynos5433_decon.h
index b26511a..ef8e2a8 100644
--- a/include/video/exynos5433_decon.h
+++ b/include/video/exynos5433_decon.h
@@ -89,6 +89,7 @@
 #define VIDCON0_ENVID_F			(1 << 0)
 
 /* VIDOUTCON0 */
+#define VIDOUT_INTERLACE_FIELD_F	(1 << 29)
 #define VIDOUT_INTERLACE_EN_F		(1 << 28)
 #define VIDOUT_LCD_ON			(1 << 24)
 #define VIDOUT_IF_F_MASK		(0x3 << 20)
-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1563600 — Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields

On Fri, Jan 20, 2017 at 07:52:24AM +0100, Andrzej Hajda wrote:
> In case of interlace mode irq is generated for odd and even fields, but
> vblank should be signaled only for the last emitted field.

I'm pretty sure most drivers signal it for both fields. At least i915
does.

> 
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> ---
>  drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 7 +++++++
>  include/video/exynos5433_decon.h              | 1 +
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> index 46434ba9..ad8b93a 100644
> --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> @@ -591,6 +591,13 @@ static irqreturn_t decon_irq_handler(int irq, void *dev_id)
>  
>  	if (val) {
>  		writel(val, ctx->addr + DECON_VIDINTCON1);
> +		if (ctx->out_type & IFTYPE_HDMI) {
> +			val = readl(ctx->addr + DECON_VIDOUTCON0);
> +			val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
> +			if (val ==
> +			    (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
> +				return IRQ_HANDLED;
> +		}
>  		drm_crtc_handle_vblank(&ctx->crtc->base);
>  	}
>  
> diff --git a/include/video/exynos5433_decon.h b/include/video/exynos5433_decon.h
> index b26511a..ef8e2a8 100644
> --- a/include/video/exynos5433_decon.h
> +++ b/include/video/exynos5433_decon.h
> @@ -89,6 +89,7 @@
>  #define VIDCON0_ENVID_F			(1 << 0)
>  
>  /* VIDOUTCON0 */
> +#define VIDOUT_INTERLACE_FIELD_F	(1 << 29)
>  #define VIDOUT_INTERLACE_EN_F		(1 << 28)
>  #define VIDOUT_LCD_ON			(1 << 24)
>  #define VIDOUT_IF_F_MASK		(0x3 << 20)
> -- 
> 2.7.4
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Ville Syrjälä
Intel OTC

[toc] | [prev] | [next] | [standalone]

#1564805 — Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields

On 20.01.2017 14:55, Ville Syrjälä wrote:
> On Fri, Jan 20, 2017 at 07:52:24AM +0100, Andrzej Hajda wrote:
>> In case of interlace mode irq is generated for odd and even fields, but
>> vblank should be signaled only for the last emitted field.
> I'm pretty sure most drivers signal it for both fields. At least i915
> does.

The question is which behavior is correct? I have not found any clear
statement in the documentation, or drm core code.
I have guessed that since vblank event is used to signal end of scan-out
of buffer it should be called after scan-out of whole buffer - in case
of interlaced mode after scan-out of 2nd field.
Maybe my assumption is wrong, in such case this patch should be dropped
and mixer driver also should be fixed, but before doing that it would be
good to know for sure how it should be handled correctly.

Regards
Andrzej

[toc] | [prev] | [next] | [standalone]

#1566633 — Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields

On Mon, Jan 23, 2017 at 10:15:16AM +0100, Andrzej Hajda wrote:
> On 20.01.2017 14:55, Ville Syrjälä wrote:
> > On Fri, Jan 20, 2017 at 07:52:24AM +0100, Andrzej Hajda wrote:
> >> In case of interlace mode irq is generated for odd and even fields, but
> >> vblank should be signaled only for the last emitted field.
> > I'm pretty sure most drivers signal it for both fields. At least i915
> > does.
> 
> The question is which behavior is correct? I have not found any clear
> statement in the documentation, or drm core code.

That's very typical for us unfortunately.

I would say what we should do what i915 does. It allows more flexibility
in how you use the hardware. Eg. then you can actually scan out
interlaced material to an interlaced display and not mess up the fields,
and you can also do 3:2 pulldown type of stuff. Or you can even just
stuff progressive frames down the pipe at field rate.

One problem with interlaced stuff is that we don't have any field
indication in the events, nor do we have a way to flip on a specific
field. I tried to specify the latter for the SETPLANE ioctl way
back when, but it didn't end up being implemented and now we would
need something different for atomic.

> I have guessed that since vblank event is used to signal end of scan-out
> of buffer it should be called after scan-out of whole buffer - in case
> of interlaced mode after scan-out of 2nd field.

Each field has a proper vertical blanking interval, so you'd just end up
totally wasting one of them.

> Maybe my assumption is wrong, in such case this patch should be dropped
> and mixer driver also should be fixed, but before doing that it would be
> good to know for sure how it should be handled correctly.
> 
> Regards
> Andrzej

-- 
Ville Syrjälä
Intel OTC

[toc] | [prev] | [next] | [standalone]

#1567168 — Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields

On 25.01.2017 15:06, Ville Syrjälä wrote:
> On Mon, Jan 23, 2017 at 10:15:16AM +0100, Andrzej Hajda wrote:
>> On 20.01.2017 14:55, Ville Syrjälä wrote:
>>> On Fri, Jan 20, 2017 at 07:52:24AM +0100, Andrzej Hajda wrote:
>>>> In case of interlace mode irq is generated for odd and even fields, but
>>>> vblank should be signaled only for the last emitted field.
>>> I'm pretty sure most drivers signal it for both fields. At least i915
>>> does.
>> The question is which behavior is correct? I have not found any clear
>> statement in the documentation, or drm core code.
> That's very typical for us unfortunately.
>
> I would say what we should do what i915 does. It allows more flexibility
> in how you use the hardware. Eg. then you can actually scan out
> interlaced material to an interlaced display and not mess up the fields,
> and you can also do 3:2 pulldown type of stuff. Or you can even just
> stuff progressive frames down the pipe at field rate.
>
> One problem with interlaced stuff is that we don't have any field
> indication in the events, nor do we have a way to flip on a specific
> field. I tried to specify the latter for the SETPLANE ioctl way
> back when, but it didn't end up being implemented and now we would
> need something different for atomic.
>
>> I have guessed that since vblank event is used to signal end of scan-out
>> of buffer it should be called after scan-out of whole buffer - in case
>> of interlaced mode after scan-out of 2nd field.
> Each field has a proper vertical blanking interval, so you'd just end up
> totally wasting one of them.

The problem in this particular case is that hardware does not allow to
change buffers between fields, or more precisely it updates its internal
registers after 2nd field - ie after reading full frame.
I am still investigating the issue, but it is possible this limitation
cannot be overcome.

Regards
Andrzej

>
>> Maybe my assumption is wrong, in such case this patch should be dropped
>> and mixer driver also should be fixed, but before doing that it would be
>> good to know for sure how it should be handled correctly.
>>
>> Regards
>> Andrzej

[toc] | [prev] | [next] | [standalone]

#1567317 — Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields

On Thu, Jan 26, 2017 at 09:22:27AM +0100, Andrzej Hajda wrote:
> On 25.01.2017 15:06, Ville Syrjälä wrote:
> > On Mon, Jan 23, 2017 at 10:15:16AM +0100, Andrzej Hajda wrote:
> >> On 20.01.2017 14:55, Ville Syrjälä wrote:
> >>> On Fri, Jan 20, 2017 at 07:52:24AM +0100, Andrzej Hajda wrote:
> >>>> In case of interlace mode irq is generated for odd and even fields, but
> >>>> vblank should be signaled only for the last emitted field.
> >>> I'm pretty sure most drivers signal it for both fields. At least i915
> >>> does.
> >> The question is which behavior is correct? I have not found any clear
> >> statement in the documentation, or drm core code.
> > That's very typical for us unfortunately.
> >
> > I would say what we should do what i915 does. It allows more flexibility
> > in how you use the hardware. Eg. then you can actually scan out
> > interlaced material to an interlaced display and not mess up the fields,
> > and you can also do 3:2 pulldown type of stuff. Or you can even just
> > stuff progressive frames down the pipe at field rate.
> >
> > One problem with interlaced stuff is that we don't have any field
> > indication in the events, nor do we have a way to flip on a specific
> > field. I tried to specify the latter for the SETPLANE ioctl way
> > back when, but it didn't end up being implemented and now we would
> > need something different for atomic.
> >
> >> I have guessed that since vblank event is used to signal end of scan-out
> >> of buffer it should be called after scan-out of whole buffer - in case
> >> of interlaced mode after scan-out of 2nd field.
> > Each field has a proper vertical blanking interval, so you'd just end up
> > totally wasting one of them.
> 
> The problem in this particular case is that hardware does not allow to
> change buffers between fields, or more precisely it updates its internal
> registers after 2nd field - ie after reading full frame.

Oh. That's a rather odd piece of hw then. In that case it might indeed
be better to not signal vblank for the field that can't do the flip.

> I am still investigating the issue, but it is possible this limitation
> cannot be overcome.
> 
> Regards
> Andrzej
> 
> >
> >> Maybe my assumption is wrong, in such case this patch should be dropped
> >> and mixer driver also should be fixed, but before doing that it would be
> >> good to know for sure how it should be handled correctly.
> >>
> >> Regards
> >> Andrzej
> 

-- 
Ville Syrjälä
Intel OTC

[toc] | [prev] | [next] | [standalone]

#1563331 — [PATCH 3/7] drm/exynos/hdmi: fix PLL for 27MHz settings

Current settings for 27MHz and 27.027MHz do not work. Use the settings from
vendor code instead.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
---
 drivers/gpu/drm/exynos/exynos_hdmi.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 223b872..a73b192 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -509,9 +509,9 @@ static const struct hdmiphy_config hdmiphy_5433_configs[] = {
 	{
 		.pixel_clock = 27000000,
 		.conf = {
-			0x01, 0x51, 0x22, 0x51, 0x08, 0xfc, 0x88, 0x46,
-			0x72, 0x50, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5,
-			0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
+			0x01, 0x51, 0x2d, 0x75, 0x01, 0x00, 0x88, 0x02,
+			0x72, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
+			0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 			0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 		},
 	},
@@ -519,9 +519,9 @@ static const struct hdmiphy_config hdmiphy_5433_configs[] = {
 		.pixel_clock = 27027000,
 		.conf = {
 			0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3,
-			0x71, 0x50, 0x24, 0x14, 0x24, 0x0f, 0x7c, 0xa5,
-			0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
-			0x28, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
+			0x71, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
+			0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
+			0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 		},
 	},
 	{
-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1563332 — [PATCH 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes

Ultra HD modes requires clock ticking at increased rate.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index f120d99..314d928 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -764,6 +764,9 @@
 			clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
 				      "aclk_xiu_decon0x", "pclk_smmu_decon0x",
 				      "sclk_decon_vclk", "sclk_decon_eclk";
+			assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+			assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, <0>, <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+			assigned-clock-rates = <0>, <400000000>;
 			samsung,disp-sysreg = <&syscon_disp>;
 			interrupt-names = "fifo", "vsync", "lcd_sys";
 			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1563694 — Re: [PATCH 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes

On Fri, Jan 20, 2017 at 07:52:25AM +0100, Andrzej Hajda wrote:
> Ultra HD modes requires clock ticking at increased rate.
> 
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index f120d99..314d928 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -764,6 +764,9 @@
>  			clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
>  				      "aclk_xiu_decon0x", "pclk_smmu_decon0x",
>  				      "sclk_decon_vclk", "sclk_decon_eclk";
> +			assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
> +			assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, <0>, <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
> +			assigned-clock-rates = <0>, <400000000>;

Lines got too long, please split them.

Best regards,
Krzysztof

>  			samsung,disp-sysreg = <&syscon_disp>;
>  			interrupt-names = "fifo", "vsync", "lcd_sys";
>  			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
> -- 
> 2.7.4
> 

[toc] | [prev] | [next] | [standalone]

#1564741 — [PATCH v2 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes

Ultra HD modes requires clock ticking at increased rate.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index f120d99..4d28e93 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -764,6 +764,17 @@
 			clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
 				      "aclk_xiu_decon0x", "pclk_smmu_decon0x",
 				      "sclk_decon_vclk", "sclk_decon_eclk";
+			assigned-clocks =
+				<&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
+				<&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
+				<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
+				<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+			assigned-clock-parents =
+				<&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
+				<0>,
+				<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
+				<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+			assigned-clock-rates = <0>, <400000000>;
 			samsung,disp-sysreg = <&syscon_disp>;
 			interrupt-names = "fifo", "vsync", "lcd_sys";
 			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1564780 — Re: [PATCH v2 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes

Hi Andrzej,

On 2017-01-23 08:56, Andrzej Hajda wrote:
> Ultra HD modes requires clock ticking at increased rate.
>
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> ---
>   arch/arm64/boot/dts/exynos/exynos5433.dtsi | 11 +++++++++++
>   1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index f120d99..4d28e93 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi

I think that exynos5433-tm2-common.dtsi is a better place for such 
definitions.
They can be also moved to &cmu_disp node to match convention for the clocks
configuration used on particular board.

> @@ -764,6 +764,17 @@
>   			clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
>   				      "aclk_xiu_decon0x", "pclk_smmu_decon0x",
>   				      "sclk_decon_vclk", "sclk_decon_eclk";
> +			assigned-clocks =
> +				<&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
> +				<&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
> +				<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
> +				<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
> +			assigned-clock-parents =
> +				<&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
> +				<0>,
> +				<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
> +				<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
> +			assigned-clock-rates = <0>, <400000000>;
>   			samsung,disp-sysreg = <&syscon_disp>;
>   			interrupt-names = "fifo", "vsync", "lcd_sys";
>   			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

[toc] | [prev] | [next] | [standalone]

#1564837 — [PATCH v3 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes

Ultra HD modes requires clock ticking at increased rate.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
---
v2: long lines wrapped
v3: moved assigned clocks to cmu_disp node in tm2-common
---
 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index cd8847b..5f1e172 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -217,6 +217,18 @@
 	assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
 };
 
+&cmu_disp {
+	assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
+			  <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
+			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
+			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+	assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
+				 <0>,
+				 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
+				 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+	assigned-clock-rates = <0>, <400000000>;
+};
+
 &cmu_fsys {
 	assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
 		<&cmu_top CLK_MOUT_SCLK_USBHOST30>,
-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1565117 — Re: [PATCH v3 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes

On Mon, Jan 23, 2017 at 11:05:49AM +0100, Andrzej Hajda wrote:
> Ultra HD modes requires clock ticking at increased rate.
> 
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> ---
> v2: long lines wrapped
> v3: moved assigned clocks to cmu_disp node in tm2-common
> ---
>  arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 

Thanks, applied.

Best regards,
Krzysztof

[toc] | [prev] | [next] | [standalone]

#1563673 — Re: [PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support to Exynos5433

On Fri, Jan 20, 2017 at 07:52:18AM +0100, Andrzej Hajda wrote:
> Hi Inki,
> 
> This patchset adds support for UltraHD and intrelace modes on DECON and HDMI
> drivers of Exynos5433 chipset. To fully support it on TM2(e) platforms MHL
> patches are alse required which will be posted in separate patchset.
> 
> Krzysztof, DTS patch do not depend on the previous patches, so there is
> no need to synchronize branches.

Thanks for noticing. Appreciated!

Best regards,
Krzysztof

[toc] | [prev] | [standalone]

Back to top | Article view | linux.kernel

csiph-web