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Groups > linux.kernel > #1563332
| From | Andrzej Hajda <a.hajda@samsung.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes |
| Date | 2017-01-20 08:00 +0100 |
| Message-ID | <t1Bl0-3Ul-35@gated-at.bofh.it> (permalink) |
| References | <t1BkZ-3Ul-3@gated-at.bofh.it> <t1Bl0-3Ul-37@gated-at.bofh.it> <t1BkZ-3Ul-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Ultra HD modes requires clock ticking at increased rate. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index f120d99..314d928 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -764,6 +764,9 @@ clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x", "pclk_smmu_decon0x", "sclk_decon_vclk", "sclk_decon_eclk"; + assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; + assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, <0>, <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; + assigned-clock-rates = <0>, <400000000>; samsung,disp-sysreg = <&syscon_disp>; interrupt-names = "fifo", "vsync", "lcd_sys"; interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, -- 2.7.4
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[PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support to Exynos5433 Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
[PATCH 1/7] drm/exynos/hdmi: add 297MHz pixel clock support Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
[PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Ville Syrjälä <ville.syrjala@linux.intel.com> - 2017-01-20 15:00 +0100
Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda <a.hajda@samsung.com> - 2017-01-23 10:20 +0100
Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Ville Syrjälä <ville.syrjala@linux.intel.com> - 2017-01-25 15:10 +0100
Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda <a.hajda@samsung.com> - 2017-01-26 09:30 +0100
Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Ville Syrjälä <ville.syrjala@linux.intel.com> - 2017-01-26 11:50 +0100
[PATCH 3/7] drm/exynos/hdmi: fix PLL for 27MHz settings Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
[PATCH 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
Re: [PATCH 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-20 16:00 +0100
[PATCH v2 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Andrzej Hajda <a.hajda@samsung.com> - 2017-01-23 09:00 +0100
Re: [PATCH v2 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Marek Szyprowski <m.szyprowski@samsung.com> - 2017-01-23 10:10 +0100
[PATCH v3 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Andrzej Hajda <a.hajda@samsung.com> - 2017-01-23 11:10 +0100
Re: [PATCH v3 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-23 17:40 +0100
Re: [PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support to Exynos5433 Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-20 15:50 +0100
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