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Groups > linux.kernel > #1563331
| From | Andrzej Hajda <a.hajda@samsung.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 3/7] drm/exynos/hdmi: fix PLL for 27MHz settings |
| Date | 2017-01-20 08:00 +0100 |
| Message-ID | <t1Bl0-3Ul-29@gated-at.bofh.it> (permalink) |
| References | <t1BkZ-3Ul-3@gated-at.bofh.it> <t1Bl0-3Ul-31@gated-at.bofh.it> <t1BkZ-3Ul-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Current settings for 27MHz and 27.027MHz do not work. Use the settings from
vendor code instead.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 223b872..a73b192 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -509,9 +509,9 @@ static const struct hdmiphy_config hdmiphy_5433_configs[] = {
{
.pixel_clock = 27000000,
.conf = {
- 0x01, 0x51, 0x22, 0x51, 0x08, 0xfc, 0x88, 0x46,
- 0x72, 0x50, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5,
- 0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
+ 0x01, 0x51, 0x2d, 0x75, 0x01, 0x00, 0x88, 0x02,
+ 0x72, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
+ 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
},
},
@@ -519,9 +519,9 @@ static const struct hdmiphy_config hdmiphy_5433_configs[] = {
.pixel_clock = 27027000,
.conf = {
0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3,
- 0x71, 0x50, 0x24, 0x14, 0x24, 0x0f, 0x7c, 0xa5,
- 0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
- 0x28, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
+ 0x71, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
+ 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
+ 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
},
},
{
--
2.7.4
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[PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support to Exynos5433 Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
[PATCH 1/7] drm/exynos/hdmi: add 297MHz pixel clock support Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
[PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Ville Syrjälä <ville.syrjala@linux.intel.com> - 2017-01-20 15:00 +0100
Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda <a.hajda@samsung.com> - 2017-01-23 10:20 +0100
Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Ville Syrjälä <ville.syrjala@linux.intel.com> - 2017-01-25 15:10 +0100
Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda <a.hajda@samsung.com> - 2017-01-26 09:30 +0100
Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Ville Syrjälä <ville.syrjala@linux.intel.com> - 2017-01-26 11:50 +0100
[PATCH 3/7] drm/exynos/hdmi: fix PLL for 27MHz settings Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
[PATCH 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
Re: [PATCH 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-20 16:00 +0100
[PATCH v2 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Andrzej Hajda <a.hajda@samsung.com> - 2017-01-23 09:00 +0100
Re: [PATCH v2 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Marek Szyprowski <m.szyprowski@samsung.com> - 2017-01-23 10:10 +0100
[PATCH v3 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Andrzej Hajda <a.hajda@samsung.com> - 2017-01-23 11:10 +0100
Re: [PATCH v3 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-23 17:40 +0100
Re: [PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support to Exynos5433 Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-20 15:50 +0100
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