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Groups > linux.kernel > #1563600
| From | Ville Syrjälä <ville.syrjala@linux.intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields |
| Date | 2017-01-20 15:00 +0100 |
| Message-ID | <t1HTs-7WH-15@gated-at.bofh.it> (permalink) |
| References | <t1BkZ-3Ul-3@gated-at.bofh.it> <t1BkZ-3Ul-25@gated-at.bofh.it> <t1BkZ-3Ul-23@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Fri, Jan 20, 2017 at 07:52:24AM +0100, Andrzej Hajda wrote:
> In case of interlace mode irq is generated for odd and even fields, but
> vblank should be signaled only for the last emitted field.
I'm pretty sure most drivers signal it for both fields. At least i915
does.
>
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> ---
> drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 7 +++++++
> include/video/exynos5433_decon.h | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> index 46434ba9..ad8b93a 100644
> --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> @@ -591,6 +591,13 @@ static irqreturn_t decon_irq_handler(int irq, void *dev_id)
>
> if (val) {
> writel(val, ctx->addr + DECON_VIDINTCON1);
> + if (ctx->out_type & IFTYPE_HDMI) {
> + val = readl(ctx->addr + DECON_VIDOUTCON0);
> + val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
> + if (val ==
> + (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
> + return IRQ_HANDLED;
> + }
> drm_crtc_handle_vblank(&ctx->crtc->base);
> }
>
> diff --git a/include/video/exynos5433_decon.h b/include/video/exynos5433_decon.h
> index b26511a..ef8e2a8 100644
> --- a/include/video/exynos5433_decon.h
> +++ b/include/video/exynos5433_decon.h
> @@ -89,6 +89,7 @@
> #define VIDCON0_ENVID_F (1 << 0)
>
> /* VIDOUTCON0 */
> +#define VIDOUT_INTERLACE_FIELD_F (1 << 29)
> #define VIDOUT_INTERLACE_EN_F (1 << 28)
> #define VIDOUT_LCD_ON (1 << 24)
> #define VIDOUT_IF_F_MASK (0x3 << 20)
> --
> 2.7.4
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Ville Syrjälä
Intel OTC
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[PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support to Exynos5433 Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
[PATCH 1/7] drm/exynos/hdmi: add 297MHz pixel clock support Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
[PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Ville Syrjälä <ville.syrjala@linux.intel.com> - 2017-01-20 15:00 +0100
Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda <a.hajda@samsung.com> - 2017-01-23 10:20 +0100
Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Ville Syrjälä <ville.syrjala@linux.intel.com> - 2017-01-25 15:10 +0100
Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda <a.hajda@samsung.com> - 2017-01-26 09:30 +0100
Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Ville Syrjälä <ville.syrjala@linux.intel.com> - 2017-01-26 11:50 +0100
[PATCH 3/7] drm/exynos/hdmi: fix PLL for 27MHz settings Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
[PATCH 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
Re: [PATCH 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-20 16:00 +0100
[PATCH v2 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Andrzej Hajda <a.hajda@samsung.com> - 2017-01-23 09:00 +0100
Re: [PATCH v2 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Marek Szyprowski <m.szyprowski@samsung.com> - 2017-01-23 10:10 +0100
[PATCH v3 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Andrzej Hajda <a.hajda@samsung.com> - 2017-01-23 11:10 +0100
Re: [PATCH v3 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-23 17:40 +0100
Re: [PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support to Exynos5433 Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-20 15:50 +0100
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