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Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields

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On 20.01.2017 14:55, Ville Syrjälä wrote:
> On Fri, Jan 20, 2017 at 07:52:24AM +0100, Andrzej Hajda wrote:
>> In case of interlace mode irq is generated for odd and even fields, but
>> vblank should be signaled only for the last emitted field.
> I'm pretty sure most drivers signal it for both fields. At least i915
> does.

The question is which behavior is correct? I have not found any clear
statement in the documentation, or drm core code.
I have guessed that since vblank event is used to signal end of scan-out
of buffer it should be called after scan-out of whole buffer - in case
of interlaced mode after scan-out of 2nd field.
Maybe my assumption is wrong, in such case this patch should be dropped
and mixer driver also should be fixed, but before doing that it would be
good to know for sure how it should be handled correctly.

Regards
Andrzej

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[PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support to  Exynos5433 Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
  [PATCH 1/7] drm/exynos/hdmi: add 297MHz pixel clock support Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
  [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
    Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd  fields Ville Syrjälä <ville.syrjala@linux.intel.com> - 2017-01-20 15:00 +0100
      Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda <a.hajda@samsung.com> - 2017-01-23 10:20 +0100
        Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd  fields Ville Syrjälä <ville.syrjala@linux.intel.com> - 2017-01-25 15:10 +0100
          Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda <a.hajda@samsung.com> - 2017-01-26 09:30 +0100
            Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd  fields Ville Syrjälä <ville.syrjala@linux.intel.com> - 2017-01-26 11:50 +0100
  [PATCH 3/7] drm/exynos/hdmi: fix PLL for 27MHz settings Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
  [PATCH 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD  modes Andrzej Hajda <a.hajda@samsung.com> - 2017-01-20 08:00 +0100
    Re: [PATCH 7/7] arm64: dts: exynos: configure TV path clocks for  Ultra HD modes Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-20 16:00 +0100
      [PATCH v2 7/7] arm64: dts: exynos: configure TV path clocks for Ultra  HD modes Andrzej Hajda <a.hajda@samsung.com> - 2017-01-23 09:00 +0100
        Re: [PATCH v2 7/7] arm64: dts: exynos: configure TV path clocks for  Ultra HD modes Marek Szyprowski <m.szyprowski@samsung.com> - 2017-01-23 10:10 +0100
          [PATCH v3 7/7] arm64: dts: exynos: configure TV path clocks for Ultra  HD modes Andrzej Hajda <a.hajda@samsung.com> - 2017-01-23 11:10 +0100
            Re: [PATCH v3 7/7] arm64: dts: exynos: configure TV path clocks for  Ultra HD modes Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-23 17:40 +0100
  Re: [PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support  to Exynos5433 Krzysztof Kozlowski <krzk@kernel.org> - 2017-01-20 15:50 +0100

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