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Groups > linux.kernel > #1384947
| From | Penny Chiu <pchiu@nvidia.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 09/11] arm64: tegra: Add DFLL clock node on Jetson TX1 |
| Date | 2016-04-22 12:40 +0200 |
| Message-ID | <rqGFc-vG-7@gated-at.bofh.it> (permalink) |
| References | <rqGFb-vG-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Add DFLL clock device-tree node for Tegra210 DFLL IP block.
Signed-off-by: Penny Chiu <pchiu@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 16 ++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 15 +++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
index 9d02db2..5cf07f2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
@@ -43,6 +43,22 @@
};
};
+ dfll: clock@70110000 {
+ status = "okay";
+
+ reg = <0x0 0x70110000 0x0 0x400>;
+ vdd-cpu-supply = <&cpu_ovr_reg>;
+ nvidia,pwm-to-pmic;
+ nvidia,init-uv = <1000000>;
+ nvidia,align-step-uv = <19200>; /* 19.2mv */
+ nvidia,sample-rate = <25000>;
+ nvidia,droop-ctrl = <0x00000f00>;
+ nvidia,force-mode = <1>;
+ nvidia,cf = <6>;
+ nvidia,ci = <0>;
+ nvidia,cg = <2>;
+ };
+
pwm_dfll: pwm@70110000 {
compatible = "nvidia,tegra210-dfll-pwm";
reg = <0x0 0x70110000 0x0 0x400>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index ba0462e..204d9cd 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -3,6 +3,7 @@
#include <dt-bindings/memory/tegra210-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/tegra210-car.h>
/ {
compatible = "nvidia,tegra210";
@@ -684,6 +685,20 @@
status = "disabled";
};
+ dfll: clock@70110000 {
+ compatible = "nvidia,tegra210-dfll";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
+ <&tegra_car TEGRA210_CLK_DFLL_REF>,
+ <&tegra_car TEGRA210_CLK_I2C5>;
+ clock-names = "soc", "ref", "i2c";
+ resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
+ reset-names = "dvco";
+ #clock-cells = <0>;
+ clock-output-names = "dfllCPU_out";
+ status = "disabled";
+ };
+
usb@7d000000 {
compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
reg = <0x0 0x7d000000 0x0 0x4000>;
--
2.8.1
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[PATCH 00/11] arm64: tegra: Add Tegra DFLL for Tegra210 Jetson TX1 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
[PATCH 09/11] arm64: tegra: Add DFLL clock node on Jetson TX1 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 09/11] arm64: tegra: Add DFLL clock node on Jetson TX1 Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:30 +0200
[PATCH 08/11] arm64: tegra: Add PWM regulator for CPU rail on Jetson TX1 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
[PATCH 11/11] arm64: config: Enable CPUFreq-DT, Tegra DFLL PWM, and PWM regulator Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
[PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Jon Hunter <jonathanh@nvidia.com> - 2016-04-22 13:50 +0200
Re: [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:30 +0200
Re: [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Jon Hunter <jonathanh@nvidia.com> - 2016-04-22 15:40 +0200
[PATCH 06/11] clk: tegra: dfll: Add PWM inferface Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
[PATCH 02/11] clk: tegra: dfll: Move SoC specific data into of_device_id Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 02/11] clk: tegra: dfll: Move SoC specific data into of_device_id Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:10 +0200
[PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210 Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:20 +0200
[PATCH 01/11] clk: tegra: dfll: Fix voltage comparison Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
[PATCH 05/11] pwm: tegra-dfll: Add driver for Tegra DFLL PWM controller Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 05/11] pwm: tegra-dfll: Add driver for Tegra DFLL PWM controller Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:00 +0200
[PATCH 04/11] clk: tegra: Add Tegra210 support in DFLL driver Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 04/11] clk: tegra: Add Tegra210 support in DFLL driver Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:20 +0200
[PATCH 07/11] cpufreq: tegra124: Add Tegra210 support Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 07/11] cpufreq: tegra124: Add Tegra210 support Viresh Kumar <viresh.kumar@linaro.org> - 2016-04-22 13:10 +0200
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