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[PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210

From Penny Chiu <pchiu@nvidia.com>
Newsgroups linux.kernel
Subject [PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210
Date 2016-04-22 12:40 +0200
Message-ID <rqGFc-vG-31@gated-at.bofh.it> (permalink)
References <rqGFb-vG-1@gated-at.bofh.it>
Organization linux.* mail to news gateway

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The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block.  This reset line is asserted upon SoC
reset.  Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and writes to the
DFLL IP block will complete.

Signed-off-by: Penny Chiu <pchiu@nvidia.com>
---
 drivers/clk/tegra/clk-tegra210.c         | 68 ++++++++++++++++++++++++++++++++
 include/dt-bindings/reset/tegra210-car.h | 12 ++++++
 2 files changed, 80 insertions(+)
 create mode 100644 include/dt-bindings/reset/tegra210-car.h

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index d3709b1..3d70b38 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -24,6 +24,7 @@
 #include <linux/export.h>
 #include <linux/clk/tegra.h>
 #include <dt-bindings/clock/tegra210-car.h>
+#include <dt-bindings/reset/tegra210-car.h>
 
 #include "clk.h"
 #include "clk-id.h"
@@ -39,6 +40,9 @@
 #define CLK_SOURCE_CSITE 0x1d4
 #define CLK_SOURCE_EMC 0x19c
 
+#define RST_DFLL_DVCO 0x2f4
+#define DVFS_DFLL_RESET_SHIFT 0
+
 #define PLLC_BASE 0x80
 #define PLLC_OUT 0x84
 #define PLLC_MISC0 0x88
@@ -2781,6 +2785,68 @@ static void __init tegra210_clock_apply_init_table(void)
 }
 
 /**
+ * tegra210_car_barrier - wait for pending writes to the CAR to complete
+ *
+ * Wait for any outstanding writes to the CAR MMIO space from this CPU
+ * to complete before continuing execution.  No return value.
+ */
+static void tegra210_car_barrier(void)
+{
+	readl_relaxed(clk_base + RST_DFLL_DVCO);
+}
+
+/**
+ * tegra210_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
+ *
+ * Assert the reset line of the DFLL's DVCO.  No return value.
+ */
+static void tegra210_clock_assert_dfll_dvco_reset(void)
+{
+	u32 v;
+
+	v = readl_relaxed(clk_base + RST_DFLL_DVCO);
+	v |= (1 << DVFS_DFLL_RESET_SHIFT);
+	writel_relaxed(v, clk_base + RST_DFLL_DVCO);
+	tegra210_car_barrier();
+}
+
+/**
+ * tegra210_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
+ *
+ * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
+ * operate.  No return value.
+ */
+static void tegra210_clock_deassert_dfll_dvco_reset(void)
+{
+	u32 v;
+
+	v = readl_relaxed(clk_base + RST_DFLL_DVCO);
+	v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
+	writel_relaxed(v, clk_base + RST_DFLL_DVCO);
+	tegra210_car_barrier();
+}
+
+static int tegra210_reset_assert(unsigned long id)
+{
+	if (id == TEGRA210_RST_DFLL_DVCO)
+		tegra210_clock_assert_dfll_dvco_reset();
+	else
+		return -EINVAL;
+
+	return 0;
+}
+
+static int tegra210_reset_deassert(unsigned long id)
+{
+	if (id == TEGRA210_RST_DFLL_DVCO)
+		tegra210_clock_deassert_dfll_dvco_reset();
+	else
+		return -EINVAL;
+
+	return 0;
+}
+
+/**
  * tegra210_clock_init - Tegra210-specific clock initialization
  * @np: struct device_node * of the DT node for the SoC CAR IP block
  *
@@ -2844,6 +2910,8 @@ static void __init tegra210_clock_init(struct device_node *np)
 
 	tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks,
 				  &pll_x_params);
+	tegra_init_special_resets(1, tegra210_reset_assert,
+				tegra210_reset_deassert);
 	tegra_add_of_provider(np);
 	tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
 
diff --git a/include/dt-bindings/reset/tegra210-car.h b/include/dt-bindings/reset/tegra210-car.h
new file mode 100644
index 0000000..a8632af
--- /dev/null
+++ b/include/dt-bindings/reset/tegra210-car.h
@@ -0,0 +1,12 @@
+/*
+ * This header provides Tegra210-specific constants for binding
+ * nvidia,tegra210-car.
+ */
+
+#ifndef _DT_BINDINGS_RESET_TEGRA210_CAR_H
+#define _DT_BINDINGS_RESET_TEGRA210_CAR_H
+
+#define TEGRA210_RESET(x)		(7 * 32 + (x))
+#define TEGRA210_RST_DFLL_DVCO		TEGRA210_RESET(0)
+
+#endif	/* _DT_BINDINGS_RESET_TEGRA210_CAR_H */
-- 
2.8.1

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Thread

[PATCH 00/11] arm64: tegra: Add Tegra DFLL for Tegra210 Jetson TX1 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
  [PATCH 09/11] arm64: tegra: Add DFLL clock node on Jetson TX1 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
    Re: [PATCH 09/11] arm64: tegra: Add DFLL clock node on Jetson TX1 Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:30 +0200
  [PATCH 08/11] arm64: tegra: Add PWM regulator for CPU rail on Jetson TX1 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
  [PATCH 11/11] arm64: config: Enable CPUFreq-DT, Tegra DFLL PWM, and PWM regulator Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
  [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
    Re: [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for  Tegra210 Jon Hunter <jonathanh@nvidia.com> - 2016-04-22 13:50 +0200
      Re: [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for  Tegra210 Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:30 +0200
        Re: [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for  Tegra210 Jon Hunter <jonathanh@nvidia.com> - 2016-04-22 15:40 +0200
  [PATCH 06/11] clk: tegra: dfll: Add PWM inferface Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
  [PATCH 02/11] clk: tegra: dfll: Move SoC specific data into of_device_id Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
    Re: [PATCH 02/11] clk: tegra: dfll: Move SoC specific data into  of_device_id Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:10 +0200
  [PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
    Re: [PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for  Tegra210 Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:20 +0200
  [PATCH 01/11] clk: tegra: dfll: Fix voltage comparison Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
  [PATCH 05/11] pwm: tegra-dfll: Add driver for Tegra DFLL PWM controller Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
    Re: [PATCH 05/11] pwm: tegra-dfll: Add driver for Tegra DFLL PWM  controller Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:00 +0200
  [PATCH 04/11] clk: tegra: Add Tegra210 support in DFLL driver Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
    Re: [PATCH 04/11] clk: tegra: Add Tegra210 support in DFLL driver Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:20 +0200
  [PATCH 07/11] cpufreq: tegra124: Add Tegra210 support Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
    Re: [PATCH 07/11] cpufreq: tegra124: Add Tegra210 support Viresh Kumar <viresh.kumar@linaro.org> - 2016-04-22 13:10 +0200

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