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Groups > linux.kernel > #1384944
| From | Penny Chiu <pchiu@nvidia.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 00/11] arm64: tegra: Add Tegra DFLL for Tegra210 Jetson TX1 |
| Date | 2016-04-22 12:40 +0200 |
| Message-ID | <rqGFb-vG-1@gated-at.bofh.it> (permalink) |
| Organization | linux.* mail to news gateway |
This patch series implements the DFLL/CL-DVFS clock source on Tegra210 based on Tegra124 DFLL driver, Tegra210 support on Tegra124 cpufreq driver, and exposes DFLL HW as a PWM controller and provides DFLL_PWM driver to generate PWM signals to control an OpenVReg (PWM regulator) for CPU rail. This patch series has been tested on the Jetson TX1. Penny Chiu (11): clk: tegra: dfll: Fix voltage comparison clk: tegra: dfll: Move SoC specific data into of_device_id clk: tegra: Add DFLL DVCO reset control for Tegra210 clk: tegra: Add Tegra210 support in DFLL driver pwm: tegra-dfll: Add driver for Tegra DFLL PWM controller clk: tegra: dfll: Add PWM inferface cpufreq: tegra124: Add Tegra210 support arm64: tegra: Add PWM regulator for CPU rail on Jetson TX1 arm64: tegra: Add DFLL clock node on Jetson TX1 arm64: tegra: Add clock properties on cpu0 for Tegra210 arm64: config: Enable CPUFreq-DT, Tegra DFLL PWM, and PWM regulator .../bindings/clock/nvidia,tegra124-dfll.txt | 21 +- .../bindings/pwm/nvidia,tegra-dfll-pwm.txt | 48 +++ arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 56 +++ arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 23 ++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 21 + arch/arm64/configs/defconfig | 4 + drivers/clk/tegra/Makefile | 4 +- drivers/clk/tegra/clk-dfll.c | 422 +++++++++++++++------ drivers/clk/tegra/clk-dfll.h | 1 + drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 127 ++++++- drivers/clk/tegra/clk-tegra210.c | 68 ++++ drivers/clk/tegra/cvb.c | 12 +- drivers/clk/tegra/cvb.h | 8 +- drivers/cpufreq/tegra124-cpufreq.c | 3 +- drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-tegra-dfll.c | 322 ++++++++++++++++ include/dt-bindings/reset/tegra210-car.h | 12 + include/soc/tegra/pwm-tegra-dfll.h | 27 ++ 19 files changed, 1046 insertions(+), 144 deletions(-) create mode 100644 Documentation/devicetree/bindings/pwm/nvidia,tegra-dfll-pwm.txt create mode 100644 drivers/pwm/pwm-tegra-dfll.c create mode 100644 include/dt-bindings/reset/tegra210-car.h create mode 100644 include/soc/tegra/pwm-tegra-dfll.h -- 2.8.1
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[PATCH 00/11] arm64: tegra: Add Tegra DFLL for Tegra210 Jetson TX1 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
[PATCH 09/11] arm64: tegra: Add DFLL clock node on Jetson TX1 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 09/11] arm64: tegra: Add DFLL clock node on Jetson TX1 Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:30 +0200
[PATCH 08/11] arm64: tegra: Add PWM regulator for CPU rail on Jetson TX1 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
[PATCH 11/11] arm64: config: Enable CPUFreq-DT, Tegra DFLL PWM, and PWM regulator Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
[PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Jon Hunter <jonathanh@nvidia.com> - 2016-04-22 13:50 +0200
Re: [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:30 +0200
Re: [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Jon Hunter <jonathanh@nvidia.com> - 2016-04-22 15:40 +0200
[PATCH 06/11] clk: tegra: dfll: Add PWM inferface Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
[PATCH 02/11] clk: tegra: dfll: Move SoC specific data into of_device_id Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 02/11] clk: tegra: dfll: Move SoC specific data into of_device_id Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:10 +0200
[PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210 Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:20 +0200
[PATCH 01/11] clk: tegra: dfll: Fix voltage comparison Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
[PATCH 05/11] pwm: tegra-dfll: Add driver for Tegra DFLL PWM controller Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 05/11] pwm: tegra-dfll: Add driver for Tegra DFLL PWM controller Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:00 +0200
[PATCH 04/11] clk: tegra: Add Tegra210 support in DFLL driver Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 04/11] clk: tegra: Add Tegra210 support in DFLL driver Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:20 +0200
[PATCH 07/11] cpufreq: tegra124: Add Tegra210 support Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 07/11] cpufreq: tegra124: Add Tegra210 support Viresh Kumar <viresh.kumar@linaro.org> - 2016-04-22 13:10 +0200
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