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Groups > linux.kernel > #1384950
| From | Penny Chiu <pchiu@nvidia.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 |
| Date | 2016-04-22 12:40 +0200 |
| Message-ID | <rqGFc-vG-15@gated-at.bofh.it> (permalink) |
| References | <rqGFb-vG-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Add clocks, clock-names, and clock-latency into cpu0 node.
These properties will be used by cpufreq driver.
Signed-off-by: Penny Chiu <pchiu@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 204d9cd..1a85857 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -782,6 +782,12 @@
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0>;
+ clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
+ <&tegra_car TEGRA210_CLK_PLL_X>,
+ <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
+ <&dfll>;
+ clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
+ clock-latency = <300000>;
};
cpu@1 {
--
2.8.1
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[PATCH 00/11] arm64: tegra: Add Tegra DFLL for Tegra210 Jetson TX1 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
[PATCH 09/11] arm64: tegra: Add DFLL clock node on Jetson TX1 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 09/11] arm64: tegra: Add DFLL clock node on Jetson TX1 Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:30 +0200
[PATCH 08/11] arm64: tegra: Add PWM regulator for CPU rail on Jetson TX1 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
[PATCH 11/11] arm64: config: Enable CPUFreq-DT, Tegra DFLL PWM, and PWM regulator Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
[PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Jon Hunter <jonathanh@nvidia.com> - 2016-04-22 13:50 +0200
Re: [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:30 +0200
Re: [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Jon Hunter <jonathanh@nvidia.com> - 2016-04-22 15:40 +0200
[PATCH 06/11] clk: tegra: dfll: Add PWM inferface Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
[PATCH 02/11] clk: tegra: dfll: Move SoC specific data into of_device_id Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 02/11] clk: tegra: dfll: Move SoC specific data into of_device_id Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:10 +0200
[PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210 Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210 Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:20 +0200
[PATCH 01/11] clk: tegra: dfll: Fix voltage comparison Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
[PATCH 05/11] pwm: tegra-dfll: Add driver for Tegra DFLL PWM controller Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 05/11] pwm: tegra-dfll: Add driver for Tegra DFLL PWM controller Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:00 +0200
[PATCH 04/11] clk: tegra: Add Tegra210 support in DFLL driver Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 04/11] clk: tegra: Add Tegra210 support in DFLL driver Thierry Reding <thierry.reding@gmail.com> - 2016-04-22 15:20 +0200
[PATCH 07/11] cpufreq: tegra124: Add Tegra210 support Penny Chiu <pchiu@nvidia.com> - 2016-04-22 12:40 +0200
Re: [PATCH 07/11] cpufreq: tegra124: Add Tegra210 support Viresh Kumar <viresh.kumar@linaro.org> - 2016-04-22 13:10 +0200
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