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Re: Verilog macro issue

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> module enc5(i, o);
> 	input [31:0] i;
> 	output [4:0] o;
> 	assign o[0] = |i[01:01] | |i[03:03] | |i[05:05] | |i[07:07] | 
> |i[09:09] | |i[11:11] | |i[13:13] | |i[15:15] | |i[17:17] | |i[19:19] | 
> |i[21:21] | |i[23:23] | |i[25:25] | |i[27:27] | |i[29:29] | |i[31:31];
> 	assign o[1] = |i[03:02] | |i[07:06] | |i[11:10] | |i[15:14] | 
> |i[19:18] | |i[23:22] | |i[27:26] | |i[31:30];
> 	assign o[2] = |i[07:04] | |i[15:12] | |i[23:20] | |i[31|28];
> 	assign o[3] = |i[15:08] | |i[31:24];
> 	assign o[4] = |i[31:16];
> endmodule
> 
> This produces a nicely efficient gate version on the FPGA. But I'm 
> still have real problem getting this idea expressed as a macro that 
> will let me generate any width encoder.
> 
> It's late I'm off to bed and see if any Verilog gurus will give it a go 
> while I'm in the land of nod. :)
> 
> Chris

OK, some progress here, but I'd really like to role one macro that 
could work out and assign the row 'reg' declarations. I'm not sure how 
I can get that to happen. But at least this code dosn't require me to 
remember and manually or all the bit patterns together, plus it 
compiles to nice wide or gates.

`define ENC_ROW(REG, BIT, WIDTH) \
always	 \
begin \
	integer s; \
	integer r; \
	REG = 0; \
	for (s = (2 ** BIT); s < WIDTH; s = s + (2 ** BIT) + (2 ** BIT)) \
	begin \
		for (r = s; r < (s + (2 ** BIT)); r = r + 1) \
		begin \
			REG = (REG | i[r]); \
		end \
	end \
end \
assign o[BIT] = REG;

module enc1(i, o);
	parameter BITS = 1;
	parameter WIDTH = (2 ** BITS);
	input [(WIDTH - 1):0] i;
	output [(BITS - 1):0] o;
	reg a;
	`ENC_ROW(a, 0, WIDTH)
endmodule

module enc2(i, o);
	parameter BITS = 2;
	parameter WIDTH = (2 ** BITS);
	input [(WIDTH - 1):0] i;
	output [(BITS - 1):0] o;
	reg a, b;
	`ENC_ROW(a, 0, WIDTH)
	`ENC_ROW(b, 1, WIDTH)
endmodule

module enc3(i, o);
	parameter BITS = 3;
	parameter WIDTH = (2 ** BITS);
	input [(WIDTH - 1):0] i;
	output [(BITS - 1):0] o;
	reg a, b, c;
	`ENC_ROW(a, 0, WIDTH)
	`ENC_ROW(b, 1, WIDTH)
	`ENC_ROW(c, 2, WIDTH)
endmodule

module enc4(i, o);
	parameter BITS = 4;
	parameter WIDTH = (2 ** BITS);
	input [(WIDTH - 1):0] i;
	output [(BITS - 1):0] o;
	reg a, b, c, d;
	`ENC_ROW(a, 0, WIDTH)
	`ENC_ROW(b, 1, WIDTH)
	`ENC_ROW(c, 2, WIDTH)
	`ENC_ROW(d, 3, WIDTH)
endmodule

module enc5(i, o);
	parameter BITS = 5;
	parameter WIDTH = (2 ** BITS);
	input [(WIDTH - 1):0] i;
	output [(BITS - 1):0] o;
	reg a, b, c, d, e;
	`ENC_ROW(a, 0, WIDTH)
	`ENC_ROW(b, 1, WIDTH)
	`ENC_ROW(c, 2, WIDTH)
	`ENC_ROW(d, 3, WIDTH)
	`ENC_ROW(e, 4, WIDTH)
endmodule

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Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 19:36 +0100
  Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-02 20:26 +0100
    Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 20:31 +0100
      Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 20:43 +0100
        Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 21:36 +0100
          Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 22:12 +0100
    Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 23:01 +0100
      Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-02 23:33 +0100
        Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 03:58 +0100
          Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 12:27 +0100
            Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 13:20 +0100
              Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-07 23:26 +0100
                Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-10 23:20 +0100
              Re: Verilog macro issue rickman <gnuarm@gmail.com> - 2011-04-11 10:36 -0700
  Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-11 20:16 +0100

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