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Groups > comp.lang.forth > #961

Re: Verilog macro issue

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On 2011-04-02 20:26:32 +0100, Jan Coombs said:

> On 02/04/11 19:36, Chris Hinsley wrote:
>> Hi folks, I've been a bit quiet recontly, mostly because I've been
>> heads down on learning Verilog and moving my CPU from Logisym over
>> to it.
>> 
>> I have a question that you Forth Verilog guys might be able to help
>> with.
>> 
>> I have some encoders done like the folowing:
>> 
>> module enc4(i, o);
>> input [15:0] i;
>> output [3:0] o;
>> reg [3:0] o;
>> always @(i)
>> begin
>> o = 4'h0;
>> case(i)
>> 16'b0000000000000010: o = 4'h1;
>> 16'b0000000000000100: o = 4'h2;
>> 16'b0000000000001000: o = 4'h3;
>> 16'b0000000000010000: o = 4'h4;
>> 16'b0000000000100000: o = 4'h5;
>> 16'b0000000001000000: o = 4'h6;
>> 16'b0000000010000000: o = 4'h7;
>> 16'b0000000100000000: o = 4'h8;
>> 16'b0000001000000000: o = 4'h9;
>> 16'b0000010000000000: o = 4'hA;
>> 16'b0000100000000000: o = 4'hB;
>> 16'b0001000000000000: o = 4'hC;
>> 16'b0010000000000000: o = 4'hD;
>> 16'b0100000000000000: o = 4'hE;
>> 16'b1000000000000000: o = 4'hF;
>> endcase
>> end
>> endmodule
> 
> This one is a priority encoder, so the case statement is unnecessarily 
> complex. For this, write loops to perform something like this:
> 
> o[3] = i[15]|i[14]|i[13]|i[12]|i[11]|i[10]|i[9]|i[8]
> o[2] = i[15:]|i[14]|i[13]|i[12]|i[7]|i[6]|i[5]|i[4]
> o[1] = i[15]|i[14]|i[11]|i[10]|i[7]|i[6]|i[3]|i[2]
> o[0] = i[15]|i[13]|i[11]|i[9]|i[7]|i[5]|i[3]|i[1]
> 
> 
> If you'd like to interactively test as you develop, consider using 
> MyHDL (myhdl.org), and then export your working code as Verilog or VHDL.
> 
> Jan Coombs

I didn't think it was a priority encoder ! Are you sure ? I thought 
this was a priority encoder ?

module pri_enc3(i, o);
	input [7:0] i;
	output [2:0] o;
	reg [2:0] o;
	always @(i)
	begin
		casez(i)
		8'b1???????: o = 3'h7;
		8'b01??????: o = 3'h6;
		8'b001?????: o = 3'h5;
		8'b0001????: o = 3'h4;
		8'b00001???: o = 3'h3;
		8'b000001??: o = 3'h2;
		8'b0000001?: o = 3'h1;
		8'b00000001: o = 3'h0;
		endcase
	end
endmodule

This uses a casez, and has don't care bits specfied. ?

Chris

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Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 19:36 +0100
  Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-02 20:26 +0100
    Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 20:31 +0100
      Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 20:43 +0100
        Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 21:36 +0100
          Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 22:12 +0100
    Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 23:01 +0100
      Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-02 23:33 +0100
        Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 03:58 +0100
          Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 12:27 +0100
            Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 13:20 +0100
              Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-07 23:26 +0100
                Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-10 23:20 +0100
              Re: Verilog macro issue rickman <gnuarm@gmail.com> - 2011-04-11 10:36 -0700
  Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-11 20:16 +0100

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