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Verilog macro issue

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Hi folks, I've been a bit quiet recontly, mostly because I've been 
heads down on learning Verilog and moving my CPU from Logisym over to 
it.

I have a question that you Forth Verilog guys might be able to help with.

I have some encoders done like the folowing:

module enc4(i, o);
	input [15:0] i;
	output [3:0] o;
	reg [3:0] o;
	always @(i)
	begin
		o = 4'h0;
		case(i)
		16'b0000000000000010: o = 4'h1;
		16'b0000000000000100: o = 4'h2;
		16'b0000000000001000: o = 4'h3;
		16'b0000000000010000: o = 4'h4;
		16'b0000000000100000: o = 4'h5;
		16'b0000000001000000: o = 4'h6;
		16'b0000000010000000: o = 4'h7;
		16'b0000000100000000: o = 4'h8;
		16'b0000001000000000: o = 4'h9;
		16'b0000010000000000: o = 4'hA;
		16'b0000100000000000: o = 4'hB;
		16'b0001000000000000: o = 4'hC;
		16'b0010000000000000: o = 4'hD;
		16'b0100000000000000: o = 4'hE;
		16'b1000000000000000: o = 4'hF;
		endcase
	end
endmodule

But that's all getting a bit long winded, so I thought I'd do a macro 
to generate any width encoder. But I've hit a problem with the generate 
variable comparison needing to be a constant (that's the FPGA compiler 
error). Here's the code I wanted to write. Any advice for how to 
achieve this macro ?

`define ENCODER(NAME, BITS)			\
module NAME(i, o);							\
	input [((2 ** BITS) - 1):0] i;				\
	output [(BITS - 1):0] o;					\
	genvar n;									\
	generate									\
		for (n = 0; n < (2 ** BITS); n = n + 1) \
		begin									\
			if (i == (2 ** n))					\
				assign o = n;					\
		end									\
	endgenerate								\
endmodule

`ENCODER(enc1, 1)
`ENCODER(enc2, 2)
`ENCODER(enc3, 3)

Chears.

Chris

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Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 19:36 +0100
  Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-02 20:26 +0100
    Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 20:31 +0100
      Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 20:43 +0100
        Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 21:36 +0100
          Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 22:12 +0100
    Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 23:01 +0100
      Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-02 23:33 +0100
        Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 03:58 +0100
          Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 12:27 +0100
            Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 13:20 +0100
              Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-07 23:26 +0100
                Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-10 23:20 +0100
              Re: Verilog macro issue rickman <gnuarm@gmail.com> - 2011-04-11 10:36 -0700
  Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-11 20:16 +0100

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