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Re: Verilog macro issue

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Hurrah, finally, I managed it. Gee that was tough but educational. !

Thanks Jan for putting me on the path. :)

`define ENCODER(NAME, BITS)  \
module NAME(i, o);  \
	parameter WIDTH = (2 ** BITS);  \
	input [(WIDTH - 1):0] i;  \
	output [(BITS - 1):0] o;  \
	reg [(BITS - 1):0] r;  \
	genvar row;  \
	generate  \
	begin  \
		for (row = 0; row < BITS; row = row + 1)  \
		begin : G  \
			always  \
			begin  \
				integer start;  \
				integer range;  \
				r[row] = 0;  \
				for (start = (2 ** row); start < WIDTH; start = start + (2 ** row) 
+ (2 ** row))  \
				begin  \
					for (range = start; range < (start + (2 ** row)); range = range + 1)  \
					begin  \
						r[row] = (r[row] | i[range]);  \
					end  \
				end  \
			end  \
			assign o[row] = r[row];  \
		end  \
	end  \
	endgenerate  \
endmodule

`ENCODER(enc1, 1)
`ENCODER(enc2, 2)
`ENCODER(enc3, 3)
`ENCODER(enc4, 4)
`ENCODER(enc5, 5)

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Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 19:36 +0100
  Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-02 20:26 +0100
    Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 20:31 +0100
      Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 20:43 +0100
        Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 21:36 +0100
          Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 22:12 +0100
    Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 23:01 +0100
      Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-02 23:33 +0100
        Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 03:58 +0100
          Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 12:27 +0100
            Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 13:20 +0100
              Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-07 23:26 +0100
                Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-10 23:20 +0100
              Re: Verilog macro issue rickman <gnuarm@gmail.com> - 2011-04-11 10:36 -0700
  Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-11 20:16 +0100

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