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Groups > comp.lang.forth > #977

Re: Verilog macro issue

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On 2011-04-02 23:33:40 +0100, Jan Coombs said:

> On 02/04/11 23:01, Chris Hinsley wrote:
>>> o[3] = i[15]|i[14]|i[13]|i[12]|i[11]|i[10]|i[9]|i[8]
>>> o[2] = i[15:]|i[14]|i[13]|i[12]|i[7]|i[6]|i[5]|i[4]
>>> o[1] = i[15]|i[14]|i[11]|i[10]|i[7]|i[6]|i[3]|i[2]
>>> o[0] = i[15]|i[13]|i[11]|i[9]|i[7]|i[5]|i[3]|i[1]
>> 
>> Jan, it took me a while for this to sink in. :)
> 
> Well, I've read your Verilog a few times, without the lights coming on, 
> so you still got there first.
> 
> And sorry to have short-changed you, it was only half of a slow 
> priority encoder.
> 
> Jan Coombs

module enc5(i, o);
	input [31:0] i;
	output [4:0] o;
	assign o[0] = |i[01:01] | |i[03:03] | |i[05:05] | |i[07:07] | 
|i[09:09] | |i[11:11] | |i[13:13] | |i[15:15] | |i[17:17] | |i[19:19] | 
|i[21:21] | |i[23:23] | |i[25:25] | |i[27:27] | |i[29:29] | |i[31:31];
	assign o[1] = |i[03:02] | |i[07:06] | |i[11:10] | |i[15:14] | 
|i[19:18] | |i[23:22] | |i[27:26] | |i[31:30];
	assign o[2] = |i[07:04] | |i[15:12] | |i[23:20] | |i[31|28];
	assign o[3] = |i[15:08] | |i[31:24];
	assign o[4] = |i[31:16];
endmodule

This produces a nicely efficient gate version on the FPGA. But I'm 
still have real problem getting this idea expressed as a macro that 
will let me generate any width encoder.

It's late I'm off to bed and see if any Verilog gurus will give it a go 
while I'm in the land of nod. :)

Chris

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Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 19:36 +0100
  Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-02 20:26 +0100
    Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 20:31 +0100
      Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 20:43 +0100
        Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 21:36 +0100
          Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 22:12 +0100
    Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 23:01 +0100
      Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-02 23:33 +0100
        Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 03:58 +0100
          Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 12:27 +0100
            Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 13:20 +0100
              Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-07 23:26 +0100
                Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-10 23:20 +0100
              Re: Verilog macro issue rickman <gnuarm@gmail.com> - 2011-04-11 10:36 -0700
  Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-11 20:16 +0100

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