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Re: Verilog macro issue

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On 2011-04-02 20:43:50 +0100, Chris Hinsley said:

>> 
>> I didn't think it was a priority encoder ! Are you sure ? I thought 
>> this was a priority encoder ?
> 
> Just checked on the Simulator, and it's definately _not_ a priority 
> encoder. It's an encoder with 0 as the output in any error case. !
> 
> So back to my original question. How to write the encoder generating macro. :)
> 
> Chris

This works as a macro to define priority encoders, but still not the 
same as the original encoder done with a case.

`define PRI_ENCODER(NAME, BITS)		\
module NAME(i, o);							\
	input [((2 ** BITS) - 1):0] i;				\
	output [(BITS - 1):0] o;					\
	reg [(BITS - 1):0] o;						\
	integer n;									\
	always @(i)								\
	begin : THE_LOOP						\
		o = BITS'b0;							\
		for (n = 0; n < (2 ** BITS); n = n + 1) \
		begin									\
			if (i[n])								\
			begin								\
				o = n;							\
				disable THE_LOOP;			\
			end								\
		end									\
	end										\
endmodule

`PRI_ENCODER(pri_enc3, 3)
`PRI_ENCODER(pri_enc4, 4)
`PRI_ENCODER(pri_enc5, 5)

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Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 19:36 +0100
  Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-02 20:26 +0100
    Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 20:31 +0100
      Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 20:43 +0100
        Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 21:36 +0100
          Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 22:12 +0100
    Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 23:01 +0100
      Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-02 23:33 +0100
        Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 03:58 +0100
          Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 12:27 +0100
            Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 13:20 +0100
              Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-07 23:26 +0100
                Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-10 23:20 +0100
              Re: Verilog macro issue rickman <gnuarm@gmail.com> - 2011-04-11 10:36 -0700
  Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-11 20:16 +0100

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