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Power MOSET gate capacitance variations

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  Power MOSET gate capacitance variations Piotr Wyderski <peter.pan@neverland.mil> - 2017-12-25 20:40 +0100
    Re: Power MOSET gate capacitance variations Joerg <news@analogconsultants.com> - 2017-12-25 12:08 -0800
      Re: Power MOSET gate capacitance variations Cursitor Doom <curd@notformail.com> - 2017-12-25 20:33 +0000
        Re: Power MOSET gate capacitance variations Joerg <news@analogconsultants.com> - 2017-12-25 12:41 -0800
      Re: Power MOSET gate capacitance variations Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> - 2017-12-25 13:57 -0700
        Re: Power MOSET gate capacitance variations amdx <nojunk@knology.net> - 2017-12-26 07:48 -0600
    Re: Power MOSET gate capacitance variations Chris Jones <lugnut808@spam.yahoo.com> - 2017-12-26 23:10 +1100
      Re: Power MOSET gate capacitance variations "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-12-26 09:35 -0600
        Re: Power MOSET gate capacitance variations Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> - 2017-12-26 14:57 -0500
        Re: Power MOSET gate capacitance variations Chris Jones <lugnut808@spam.yahoo.com> - 2017-12-27 22:48 +1100
      Re: Power MOSET gate capacitance variations Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> - 2017-12-26 12:58 -0500
    Re: Power MOSET gate capacitance variations Winfield Hill <hill@rowland.harvard.edu> - 2017-12-27 05:32 -0800
      Re: Power MOSET gate capacitance variations Piotr Wyderski <peter.pan@neverland.mil> - 2017-12-27 16:15 +0100
        Re: Power MOSET gate capacitance variations Winfield Hill <hill@rowland.harvard.edu> - 2017-12-27 08:47 -0800
          Re: Power MOSET gate capacitance variations "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-12-27 11:47 -0600
          Re: Power MOSET gate capacitance variations Piotr Wyderski <peter.pan@neverland.mil> - 2017-12-31 11:06 +0100
            Re: Power MOSET gate capacitance variations "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-12-31 10:43 -0600
            Re: Power MOSET gate capacitance variations Winfield Hill <hill@rowland.harvard.edu> - 2017-12-31 10:32 -0800
              Re: Power MOSET gate capacitance variations Don Kuenz <g@crcomp.net> - 2017-12-31 20:20 +0000
                Re: Power MOSET gate capacitance variations Winfield Hill <hill@rowland.harvard.edu> - 2018-01-01 17:29 -0800
                  Re: Power MOSET gate capacitance variations Don Kuenz <g@crcomp.net> - 2018-01-02 03:06 +0000
                    Re: Power MOSET gate capacitance variations Don Kuenz <g@crcomp.net> - 2018-01-03 00:18 +0000
                      Re: Power MOSET gate capacitance variations Winfield Hill <hill@rowland.harvard.edu> - 2018-01-02 18:00 -0800
                        Re: Power MOSET gate capacitance variations "Tim Williams" <tiwill@seventransistorlabs.com> - 2018-01-02 22:53 -0600
                          Re: Power MOSET gate capacitance variations krw@notreal.com - 2018-01-03 21:35 -0500

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#489296 — Power MOSET gate capacitance variations

I've just measured ten MOSFETs from the same reel and their gate
capacitance is between 1450 and 1900pF, with ~1620 being the most
common. Since capacitance = area*permittivity/distance and the
dielectric is the same SiO2, only area and distance (thickness) can
vary. I don't think the manufacturer has no control over the area,
as it is some form of litography, and thickness is proportional to
the oxide growth time, which is exactly the same within a batch.
So what is going on here?

	Best regards, Piotr

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#489297

On 2017-12-25 11:40, Piotr Wyderski wrote:
> I've just measured ten MOSFETs from the same reel and their gate
> capacitance is between 1450 and 1900pF, with ~1620 being the most
> common. Since capacitance = area*permittivity/distance and the
> dielectric is the same SiO2, only area and distance (thickness) can
> vary. I don't think the manufacturer has no control over the area,
> as it is some form of litography, and thickness is proportional to
> the oxide growth time, which is exactly the same within a batch.
> So what is going on here?
>

Thicknesses and etching processes are not completely uniform across the 
whole wafer. This gets worse as companies move to larger wafers. You can 
guarantee ratios to be very close on the same device but not when 
compared with a device two inches from that location on the wafer.

Jim Thompson could shed more light on this.

-- 
Regards, Joerg

http://www.analogconsultants.com/

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#489299

On Mon, 25 Dec 2017 12:08:37 -0800, Joerg wrote:

> Jim Thompson could shed more light on this.

Sadly Jim doesn't seem to be around today (so far at least) which is 
unfortunate. I recall many enjoyable discourses with him on this 
particular day going back 20+ years.



-- 
This message may be freely reproduced without limit or charge only via 
the Usenet protocol. Reproduction in whole or part through other 
protocols, whether for profit or not, is conditional upon a charge of 
GBP10.00 per reproduction. Publication in this manner via non-Usenet 
protocols constitutes acceptance of this condition.

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#489302

On 2017-12-25 12:33, Cursitor Doom wrote:
> On Mon, 25 Dec 2017 12:08:37 -0800, Joerg wrote:
>
>> Jim Thompson could shed more light on this.
>
> Sadly Jim doesn't seem to be around today (so far at least) which is
> unfortunate. I recall many enjoyable discourses with him on this
> particular day going back 20+ years.
>

Just let off a political rant and he'll be back, prontissimo :-)

He's got a big family and Christmas is probably not the time for him to 
be on Usenet much. I am only here over lunch, got to work later :-(

-- 
Regards, Joerg

http://www.analogconsultants.com/

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#489304

On Mon, 25 Dec 2017 12:08:37 -0800, Joerg <news@analogconsultants.com>
wrote:

>On 2017-12-25 11:40, Piotr Wyderski wrote:
>> I've just measured ten MOSFETs from the same reel and their gate
>> capacitance is between 1450 and 1900pF, with ~1620 being the most
>> common. Since capacitance = area*permittivity/distance and the
>> dielectric is the same SiO2, only area and distance (thickness) can
>> vary. I don't think the manufacturer has no control over the area,
>> as it is some form of litography, and thickness is proportional to
>> the oxide growth time, which is exactly the same within a batch.
>> So what is going on here?
>>
>
>Thicknesses and etching processes are not completely uniform across the 
>whole wafer. This gets worse as companies move to larger wafers. You can 
>guarantee ratios to be very close on the same device but not when 
>compared with a device two inches from that location on the wafer.
>
>Jim Thompson could shed more light on this.

I rarely concern myself with any matching beyond a single die.  

For multiple die matching issues I apply Thompson's "Secret Sauce" (*)
methods.

(*) Coming soon to my website: A load dump of ideas that worked, ideas
that didn't, ideas still in fermentation... no explanations... just
"stuff" that I've let my mind ramble over.  I have a copy of just
about everything I've ever tried... some dates to BC, before
computers, just on paper... If I last long enough I'll scan that it as
well... ENJOY... or fume, your choice >:-}
		
                                        ...Jim Thompson
-- 
| James E.Thompson                                 |    mens     |
| Analog Innovations                               |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
     It's what you learn, after you know it all, that counts.

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#489330

On 12/25/2017 2:57 PM, Jim Thompson wrote:
> On Mon, 25 Dec 2017 12:08:37 -0800, Joerg <news@analogconsultants.com>
> wrote:
> 
>> On 2017-12-25 11:40, Piotr Wyderski wrote:
>>> I've just measured ten MOSFETs from the same reel and their gate
>>> capacitance is between 1450 and 1900pF, with ~1620 being the most
>>> common. Since capacitance = area*permittivity/distance and the
>>> dielectric is the same SiO2, only area and distance (thickness) can
>>> vary. I don't think the manufacturer has no control over the area,
>>> as it is some form of litography, and thickness is proportional to
>>> the oxide growth time, which is exactly the same within a batch.
>>> So what is going on here?
>>>
>>
>> Thicknesses and etching processes are not completely uniform across the
>> whole wafer. This gets worse as companies move to larger wafers. You can
>> guarantee ratios to be very close on the same device but not when
>> compared with a device two inches from that location on the wafer.
>>
>> Jim Thompson could shed more light on this.
> 
> I rarely concern myself with any matching beyond a single die.
> 
> For multiple die matching issues I apply Thompson's "Secret Sauce" (*)
> methods.
> 
> (*) Coming soon to my website: A load dump of ideas that worked, ideas
> that didn't, ideas still in fermentation... no explanations... just
> "stuff" that I've let my mind ramble over.  I have a copy of just
> about everything I've ever tried... some dates to BC, before
> computers, just on paper... If I last long enough I'll scan that it as
> well... ENJOY... or fume, your choice >:-}
> 		
>                                          ...Jim Thompson
> 

   Hope you get your ideas out on the net Jim.
I had a physicist friend that worked in acoustics
all his life, sonar and such. How had a lot of secrets
that through working at a series of companies he found
others didn't know. He could build efficient transducers,
low loss vessels for research. At one company he reported
to his manager he had built a transducer that was 110%
efficient, the manager thought that was great, he said he
just walked away shaking his head and fixed their
measurement system.
  I told him several times he needed to write a book about his
subject to pass the info along. He never did, Once he closed the 
business he just went dark, didn't make contact with any one that
worked with him. He died a couple years ago and his education
went with him.
   I had a lot off fun working with Henry, I miss him.
                                         Mikek

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#489326

On 26/12/2017 06:40, Piotr Wyderski wrote:
> I've just measured ten MOSFETs from the same reel and their gate
> capacitance is between 1450 and 1900pF, with ~1620 being the most
> common. Since capacitance = area*permittivity/distance and the
> dielectric is the same SiO2, only area and distance (thickness) can
> vary. I don't think the manufacturer has no control over the area,
> as it is some form of litography, and thickness is proportional to
> the oxide growth time, which is exactly the same within a batch.
> So what is going on here?
> 
>      Best regards, Piotr

Are you measuring at the same DC gate voltage? You will see a huge 
difference between the capacitance below and above the threshold 
voltage, as one of the capacitor plates is mostly the channel, which 
turns non-conducting when the FET is off. Mosfets are used as the 
varactors in a lot of RF VCOs for e.g. cellphones.

Maybe your parts came from different wafers.

Is there a correlation between the capacitance you measured and the 
threshold voltage or gm of the same parts? This might help you to figure 
out whether the thickness of the oxide is responsible.

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#489335

"Chris Jones" <lugnut808@spam.yahoo.com> wrote in message 
news:X_q0C.73522$5Z7.30154@fx29.am4...
> Are you measuring at the same DC gate voltage? You will see a huge 
> difference between the capacitance below and above the threshold voltage, 
> as one of the capacitor plates is mostly the channel, which turns 
> non-conducting when the FET is off. Mosfets are used as the varactors in a 
> lot of RF VCOs for e.g. cellphones.

Not gate voltage actually, but drain voltage -- which could very easily be 
drifting around if it's not grounded explicitly.

The gate has very little capacitance to the channel, at least in modern 
VDMOS parts -- I can't detect a Ciss(Vgs) variation, admittedly this was 
from a crude setup.  That is to say, the linearity is better than about 10%, 
but how much better, I cannot say.

Cgs itself doesn't seem to vary with Vds, either.  Since Ciss = Cgs + Crss, 
the only varying component is due to Crss, which varies quite dramatically 
with Vds.


> Maybe your parts came from different wafers.

Yes, it's quite possible that parts end up reeled from different wafers.  I 
don't know any process reason why they'd do that (except where one wafer 
ends and the other begins), but they certainly have no reason not to, 
either.

For sure, if the ID code is different, they're from different lots or 
production dates.  Any closer than that, who knows; you'd have to ask the 
manufacturer very nicely to get them to tell you what dies, from what fabs, 
were packaged on what lines, when.


> Is there a correlation between the capacitance you measured and the 
> threshold voltage or gm of the same parts? This might help you to figure
> out whether the thickness of the oxide is responsible.

Good point!

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: https://www.seventransistorlabs.com/ 

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#489345

On 12/26/2017 10:35 AM, Tim Williams wrote:
> "Chris Jones" <lugnut808@spam.yahoo.com> wrote in message
> news:X_q0C.73522$5Z7.30154@fx29.am4...
>> Are you measuring at the same DC gate voltage? You will see a huge
>> difference between the capacitance below and above the threshold
>> voltage, as one of the capacitor plates is mostly the channel, which
>> turns non-conducting when the FET is off. Mosfets are used as the
>> varactors in a lot of RF VCOs for e.g. cellphones.
> 
> Not gate voltage actually, but drain voltage -- which could very easily
> be drifting around if it's not grounded explicitly.

Of course then C_DS wouldn't contribute to the measurement either. ;)

Cheers

Phil Hobbs


-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
https://hobbs-eo.com

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#489387

On 27/12/2017 02:35, Tim Williams wrote:
> "Chris Jones" <lugnut808@spam.yahoo.com> wrote in message 
> news:X_q0C.73522$5Z7.30154@fx29.am4...
>> Are you measuring at the same DC gate voltage? You will see a huge 
>> difference between the capacitance below and above the threshold 
>> voltage, as one of the capacitor plates is mostly the channel, which 
>> turns non-conducting when the FET is off. Mosfets are used as the 
>> varactors in a lot of RF VCOs for e.g. cellphones.
> 
> Not gate voltage actually, but drain voltage -- which could very easily 
> be drifting around if it's not grounded explicitly.
> 
> The gate has very little capacitance to the channel, at least in modern 
> VDMOS parts -- I can't detect a Ciss(Vgs) variation, admittedly this was 
> from a crude setup.  That is to say, the linearity is better than about 
> 10%, but how much better, I cannot say.
I haven't measured it on a power mosfet, I have only looked into it on 
lateral mosfets in e.g. 0.35um and 0.18um CMOS. For those, there is a 
very large variation with Vgs - more than 2:1 but I can't remember how 
much. (In the VCOs used in cellphone chips, usually the RF was applied 
to the gate and the tuning voltage was applied to the drain and source 
tied together. Normally it is a differential oscillator circuit. The 
varactors vary in capacitance greatly over one cycle of RF, going from a 
flat region of low capacitance through a steep transition to another 
flat region of high capacitance and back again, so it is more like 
pulse-width-modulating the capacitance than a linear varactor. Usually 
the varactors make up a small proportion of the tank capacitance and the 
rest is provided by a bunch of different sized pairs of capacitors with 
digitally controlled MOS switches in series, between each pair of 
capacitors. The switchable capacitors have less conversion of AM noise 
to phase noise than the MOS varactors, and smaller varactors also makes 
the tuning voltage less important as a source of phase noise.)

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#489337

On 12/26/2017 07:10 AM, Chris Jones wrote:
> On 26/12/2017 06:40, Piotr Wyderski wrote:
>> I've just measured ten MOSFETs from the same reel and their gate
>> capacitance is between 1450 and 1900pF, with ~1620 being the most
>> common. Since capacitance = area*permittivity/distance and the
>> dielectric is the same SiO2, only area and distance (thickness) can
>> vary. I don't think the manufacturer has no control over the area,
>> as it is some form of litography, and thickness is proportional to
>> the oxide growth time, which is exactly the same within a batch.
>> So what is going on here?
>>
>>      Best regards, Piotr
> 
> Are you measuring at the same DC gate voltage? You will see a huge 
> difference between the capacitance below and above the threshold 
> voltage, as one of the capacitor plates is mostly the channel, which 
> turns non-conducting when the FET is off. Mosfets are used as the 
> varactors in a lot of RF VCOs for e.g. cellphones.
> 
> Maybe your parts came from different wafers.
> 
> Is there a correlation between the capacitance you measured and the 
> threshold voltage or gm of the same parts? This might help you to figure 
> out whether the thickness of the oxide is responsible.
> 

Doping also matters.

Cheers

Phil Hobbs

-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

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#489391

Piotr Wyderski wrote...
>
> I've just measured ten MOSFETs from the same reel and their gate
> capacitance is between 1450 and 1900pF, with ~1620 being the most
> common. Since capacitance = area*permittivity/distance and the
> dielectric is the same SiO2, only area and distance (thickness) can
> vary. I don't think the manufacturer has no control over the area,
> as it is some form of litography, and thickness is proportional to
> the oxide growth time, which is exactly the same within a batch.
> So what is going on here?

 With such a high capacitance, it appears you're talking
 about a power MOSFET (it'd be nice to know the type).
 As you know, these are made with a vertical structure
 with a repeating fine-pitched laterally-stacked pattern.
 The exact height of the vertical structure is probably
 not very well controlled, and the lateral (not vertical)
 gate oxide thicknesses may also not be well controlled.
 From an Infineon note, "laterally stacked fine-pitched
 pattern of alternating arranged p- and n-areas.  The
 finer the pitch can be made, the lower the on-state
 resistance of the device will be".  Manufacturers are
 optimizing for density, not dimensional uniformity.


-- 
 Thanks,
    - Win

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#489398

Winfield Hill wrote:

>   With such a high capacitance, it appears you're talking
>   about a power MOSFET (it'd be nice to know the type).

Yes, as the title says. The part is IPD60R400CEATMA1
-- maybe not the best in its class, but dirt cheap and sufficient.

>   As you know, these are made with a vertical structure
>   with a repeating fine-pitched laterally-stacked pattern.
>   The exact height of the vertical structure is probably
>   not very well controlled, and the lateral (not vertical)
>   gate oxide thicknesses may also not be well controlled.

The origin of that spread would be obvious for parts from
different wafers, but for a given wafer the oxide thickness
should be almost constant, even if one is not willing to
control it tightly. I have no evidence that the parts are
from the same wafer, but why should the factory mix them
before encapsulation in the reel's compartments?

	Best regards, Piotr

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#489404

Piotr Wyderski wrote...
>
>Winfield Hill wrote:
>
>>   With such a high capacitance, it appears you're talking
>>   about a power MOSFET (it'd be nice to know the type).
>
>Yes, as the title says. The part is IPD60R400CEATMA1
>-- maybe not the best in its class, but dirt cheap and sufficient.
>
>>   As you know, these are made with a vertical structure
>>   with a repeating fine-pitched laterally-stacked pattern.
>>   The exact height of the vertical structure is probably
>>   not very well controlled, and the lateral (not vertical)
>>   gate oxide thicknesses may also not be well controlled.
>
>The origin of that spread would be obvious for parts from
>different wafers, but for a given wafer the oxide thickness
>should be almost constant, even if one is not willing to
>control it tightly. I have no evidence that the parts are
>from the same wafer, but why should the factory mix them
>before encapsulation in the reel's compartments?

 That's not a bad part, one of the new SuperJunction
 MOSFETs, with nice low drain capacitances.  These
 have a severe horizontally-compressed architecture,
 with everything turned 90 degrees, changing all the
 de-facto rules we're used to.


-- 
 Thanks,
    - Win

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#489408

"Winfield Hill" <hill@rowland.harvard.edu> wrote in message 
news:p20iqi02133@drn.newsguy.com...
> That's not a bad part, one of the new SuperJunction
> MOSFETs, with nice low drain capacitances.  These
> have a severe horizontally-compressed architecture,
> with everything turned 90 degrees, changing all the
> de-facto rules we're used to.

That's the kind I measured; and lower voltage (30 to 200V, say) parts seem 
to be grossly similar designs (though with not as much historical 
improvement as SJ did in one fell swoop!).  SJ also has a current limiting 
characteristic unconnected to Vgs -- transconductance tanks above about 7 or 
8V.  Reminds me of toobs, with limited cathode emission... :^)

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: https://www.seventransistorlabs.com/ 

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#489843

Winfield Hill wrote:

>   That's not a bad part, one of the new SuperJunction
>   MOSFETs, with nice low drain capacitances.

Not bad for sure, but not that shining either. 400mOhm
in 2016 is not a jaw-dropper, the 12 years older 20N60 has
just 150mOhm, but was *much* more expensive back then.

	Best regards, Piotr

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#489878

"Piotr Wyderski" <peter.pan@neverland.mil> wrote in message 
news:p2acqd$vhp$1@node1.news.atman.pl...
> Not bad for sure, but not that shining either. 400mOhm
> in 2016 is not a jaw-dropper, the 12 years older 20N60 has
> just 150mOhm, but was *much* more expensive back then.
>
> Best regards, Piotr

Well, if you just want low resistance at minimum cost, there are IRFPs for 
you.  But there's about three other critically important parameters to a 
switching circuit that you're missing there, and the total improvement is 
almost an order of magnitude between them.  All that, at nearly the same 
price.

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: https://www.seventransistorlabs.com/ 

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#489886

Piotr Wyderski wrote...
>
> Winfield Hill wrote:
>
>>   That's not a bad part, one of the new SuperJunction
>>   MOSFETs, with nice low drain capacitances.
>
> Not bad for sure, but not that shining either. 400mOhm
> in 2016 is not a jaw-dropper, the 12 years older 20N60
> has just 150mOhm, but was *much* more expensive back then.

 My continually-updated MOSFET spreadsheet (a portion
 of which appears in a few places in AoE III) now has
 over 1300 items, 380 in the 500 to 650-volt range.
 180 of these have lower Rds(on) than the IPD60R400CE.
 So it's entire a matter of choosing your tradeoffs.
 
 There are a many reasons against selecting a lower
 Rds(on): high capacitance, poor distributor stock,
 high cost, larger package, no SMT package avail...


-- 
 Thanks,
    - Win

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#489902

Winfield Hill <hill@rowland.harvard.edu> wrote:
> Piotr Wyderski wrote...
>>
>> Winfield Hill wrote:
>>
>>>   That's not a bad part, one of the new SuperJunction
>>>   MOSFETs, with nice low drain capacitances.
>>
>> Not bad for sure, but not that shining either. 400mOhm
>> in 2016 is not a jaw-dropper, the 12 years older 20N60
>> has just 150mOhm, but was *much* more expensive back then.
>
> My continually-updated MOSFET spreadsheet (a portion
> of which appears in a few places in AoE III) now has
> over 1300 items, 380 in the 500 to 650-volt range.
> 180 of these have lower Rds(on) than the IPD60R400CE.
> So it's entire a matter of choosing your tradeoffs.
>
> There are a many reasons against selecting a lower
> Rds(on): high capacitance, poor distributor stock,
> high cost, larger package, no SMT package avail...

That sounds very handy. Is it possible to purchase a copy?

Thank you,

--
Don Kuenz, KB7RPU

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#490015

Don Kuenz wrote...
>
> Winfield Hill wrote:
>> Piotr Wyderski wrote...
>>>
>>> Winfield Hill wrote:
>>>
>>>>   That's not a bad part, one of the new SuperJunction
>>>>   MOSFETs, with nice low drain capacitances.
>>>
>>> Not bad for sure, but not that shining either. 400mOhm
>>> in 2016 is not a jaw-dropper, the 12 years older 20N60
>>> has just 150mOhm, but was *much* more expensive back then.
>>
>> My continually-updated MOSFET spreadsheet (a portion
>> of which appears in a few places in AoE III) now has
>> over 1300 items, 380 in the 500 to 650-volt range.
>> 180 of these have lower Rds(on) than the IPD60R400CE.
>> So it's entire a matter of choosing your tradeoffs.
>>
>> There are a many reasons against selecting a lower
>> Rds(on): high capacitance, poor distributor stock,
>> high cost, larger package, no SMT package avail...
>
>That sounds very handy. Is it possible to purchase a copy?
>
>Thank you,

 Did you get my email?  Has it changed since your usenet
 log-on information?  Mine has, now winfieldhill@yahoo.com


-- 
 Thanks,
    - Win

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