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Re: Verilog macro issue

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From Chris Hinsley <chris.hinsley@gmail.com>
Newsgroups comp.lang.forth
Date Sat, 2 Apr 2011 22:12:41 +0100
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On 2011-04-02 21:36:23 +0100, Chris Hinsley said:

> This works as a macro to define priority encoders, but still not the 
> same as the original encoder done with a case.
> 
> `define PRI_ENCODER(NAME, BITS)		\
> module NAME(i, o);							\
> 	input [((2 ** BITS) - 1):0] i;				\
> 	output [(BITS - 1):0] o;					\
> 	reg [(BITS - 1):0] o;						\
> 	integer n;									\
> 	always @(i)								\
> 	begin : THE_LOOP						\
> 		o = BITS'b0;							\
> 		for (n = 0; n < (2 ** BITS); n = n + 1) \
> 		begin									\
> 			if (i[n])								\
> 			begin								\
> 				o = n;							\
> 				disable THE_LOOP;			\
> 			end								\
> 		end									\
> 	end										\
> endmodule
> 
> `PRI_ENCODER(pri_enc3, 3)
> `PRI_ENCODER(pri_enc4, 4)
> `PRI_ENCODER(pri_enc5, 5)

I've ended up with this, which does the correct job, but I really think 
the code sucks. There has to be a better way to do it than this ! God 
knows what the FPGA compiler will produce for this. :(

`define ENCODER(NAME, BITS)			\
module NAME(i, o);							\
	input [((2 ** BITS) - 1):0] i;				\
	output [(BITS - 1):0] o;					\
	reg [(BITS - 1):0] o;						\
	integer n, f;								\
	always @(i)								\
	begin : THE_LOOP						\
		o = BITS'b0;							\
		f = 0;									\
		for (n = 0; n < (2 ** BITS); n = n + 1) \
		begin									\
			if (i[n])								\
			begin								\
				if (f) disable THE_LOOP;	\
				f = 1;							\
			end								\
		end									\
		for (n = 0; n < (2 ** BITS); n = n + 1) \
		begin									\
			if (i[n])								\
			begin								\
				o = n;							\
				disable THE_LOOP;			\
			end								\
		end									\
	end										\
endmodule

`ENCODER(enc1, 1)
`ENCODER(enc2, 2)
`ENCODER(enc3, 3)
`ENCODER(enc4, 4)
`ENCODER(enc5, 5)

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Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 19:36 +0100
  Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-02 20:26 +0100
    Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 20:31 +0100
      Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 20:43 +0100
        Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 21:36 +0100
          Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 22:12 +0100
    Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-02 23:01 +0100
      Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-02 23:33 +0100
        Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 03:58 +0100
          Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 12:27 +0100
            Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-03 13:20 +0100
              Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-07 23:26 +0100
                Re: Verilog macro issue Jan Coombs <jan_2011-02@murray-microft.co.uk> - 2011-04-10 23:20 +0100
              Re: Verilog macro issue rickman <gnuarm@gmail.com> - 2011-04-11 10:36 -0700
  Re: Verilog macro issue Chris Hinsley <chris.hinsley@gmail.com> - 2011-04-11 20:16 +0100

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