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Re: fast divider?

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On 24/03/2026 2:20 am, john larkin wrote:
> On Mon, 23 Mar 2026 23:49:36 +1100, Bill Sloman <bill.sloman@ieee.org>
> wrote:
> 
>> On 22/03/2026 4:29 am, john larkin wrote:
>>> On Sat, 21 Mar 2026 09:38:17 -0700, Ross Finlayson
>>> <ross.a.finlayson@gmail.com> wrote:
>>>
>>>> On 03/20/2026 10:36 PM, Bill Sloman wrote:
>>>>> On 20/03/2026 4:05 am, john larkin wrote:
>>>>>> On Tue, 17 Mar 2026 22:30:01 +0000, someone
>>>>>> <cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
>>>>>>
>>>>>>> I assume these are up-counters, so the thing overflows at all 1's.
>>>>>>> Then you only have the one fast carry TPD for the MS18b overflowing
>>>>>>> to all 1s when a 1 is clocked into its LSB.  One whole clock period
>>>>>>> to clock the 1 out of the DFF and meet the setup times for what I
>>>>>>> assume is a synchronous LD and its setup for the counters. So that
>>>>>>> particular timing criticality is a DFF TPD and a LD setup TSU to
>>>>>>> reliably capture the register data. The LD TPD to CLK TSU for the
>>>>>>> LS18b counter shouldn't be a problem. This must be very speedy logic
>>>>>>> for 150MHz. Do you have a simulator that displays how much margin you
>>>>>>> have on this timing, or is it just a bunch waveforms?
>>>>>>
>>>>>> Yes, loadable up-counter with carry chain.
>>>>>>
>>>>>> This would be in an FPGA, so the diagram is just a concept. The
>>>>>> reality will be VHDL code. And the FPGA boys use the Wishbone
>>>>>> architecture and want the counter to be 32 bits, which is OK with me.
>>>>>>
>>>>>> We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
>>>>>> I expect we could do a divider in that ballpark.  The T20 is in the
>>>>>> *slow* Efinix family.
>>>>>>
>>>>>> I think the T20 has 18-bit fast carry chains.
>>>>>>
>>>>>> After the boys code this, the tools can verify timing.
>>>>>>
>>>>>> FPGAs are great, but there's a cultural gap between people who draw
>>>>>> and people who type.
>>>>>
>>>>> Can't say I've noticed that, but since I can do both, and most of the
>>>>> engineers I've hung out with could too, John Larkin may be projecting here.
>>>
>>> I base the observation on people that I work with, and lately on
>>> hundreds of people that I meet at maker-space meetups.
>>
>> You don't like hiring people with a Ph.D. My employers didn't have that
>> problem.
>>
>>> Many are kids with CE/EE degrees who don't know much about electricity and
>>> who don't have jobs.
>>>
>>> A Linked-In ad for fpga coders will get hundreds of applicants in a
>>> few days. Circuit designers, not so many. I have a couple of quick
>>> tests to find the rare kid that gets electronics.
>>
>> And presumably also test their willingness to flatter you at every
>> possible opportunity.
>>
>>>> I have a lot of interest in the Bruchla circuit as about things
>>>> like transistor nets to effect things like Fourier-style analysis.
>>>>
>>>> The Bruchla circuit among accounts of things like integrators
>>>> and differentiators, is for the middling account of dividers,
>>>> that otherwise doesn't have exactly a simple ideal circuit.
>>>>
>>>
>>> Is there some specific Bruchla frequency divider circuit?
>>>
>>> There seem to be a lot of 50-year old Bruchla circuits online. Looks
>>> like mostly audio.
>>
>> There are lots of odd ways of implementing frequency dividers.
>> Synchronous dividers can be made to work at higher frequencies than
>> ripple carry dividers, and synchronous dividers with fast carry
>> feed-forward hardware can be designed to count even faster.
>>
>> Duplicating known hardware solutions inside an FPGA can't be all that
>> difficult. There are some remarkably fast FPGAs around. When I last
>> looked they were remarkably expensive, but that was about twenty years ago.
> 
> Mostly people express intent in an HDL, basically say X=X+1, and the
> compiler makes that happen. The things inside a modern FPGA look
> nothing like 7400-series logic.

Why would they? I tended to used 100k ECL and ECLinPS when it became 
available. It was a whole lot faster that 7400-series logic, and a lot 
better at driving terminated transmission lines.

Because I worked on electron-beam microfabricators and electron-bream 
testers for some of my time at Cambridge I did have some idea of what 
the working surface of integrated circuit looked like, but not enough to 
be able to distinguish a TLL part from an ECL part  or any of the 
flavours of field programmable devices.

> I'm doing a DDS frequency synthesizer in a $9 Efinix FPGA, running at
> 250 MHz. That's neither their fastest nor their cheapest part.

We could have done that in ECLinPs in 1995. It wouldn't have been all 
that expensive.

> I'm running the DDS, driving a 5-resistor DAC and running a bunch of
> other stuff, using 24 mA at 1.2v core supply. It doesn't even feel
> warm.

Really small transistors running at 1.1V don't need to steer much 
current. Keeping all the fast bits inside an FPGA means that there isn't 
a lot of capacitance to charge and discharge either.

-- 
Bill Sloman, Sydney

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Thread

fast divider? john larkin <jl@glen--canyon.com> - 2026-03-15 11:47 -0700
  Re: fast divider? someone <cffbf4deb9142bce48974efc0e64dede@example.com> - 2026-03-17 22:30 +0000
    Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-19 10:05 -0700
      Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-21 16:36 +1100
        Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-21 07:52 -0700
          Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-22 03:00 +1100
            Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-27 11:39 -0700
              Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-28 16:44 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-28 14:38 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-29 15:52 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-29 08:18 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-30 16:42 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-30 08:00 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-31 16:35 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-31 02:40 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-31 22:30 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-31 08:14 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-04-01 15:54 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-04-01 01:06 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-04-02 02:13 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-04-01 09:12 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-04-02 14:41 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-04-02 07:53 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-04-03 02:21 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-04-02 08:57 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-04-03 04:05 +1100
          Re: fast divider? someone <cffbf4deb9142bce48974efc0e64dede@example.com> - 2026-03-26 23:30 +0000
        Re: fast divider? Ross Finlayson <ross.a.finlayson@gmail.com> - 2026-03-21 09:38 -0700
          Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-21 10:29 -0700
            Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-23 23:49 +1100
              Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-23 08:20 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-24 23:04 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-24 05:56 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-25 02:47 +1100

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