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Re: fast divider?

Cross-posted to 2 groups.

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On 28/03/2026 5:39 am, john larkin wrote:
> On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org>
> wrote:
> 
>> On 22/03/2026 1:52 am, john larkin wrote:
>>> On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org>
>>> wrote:
>>>
>>>> On 20/03/2026 4:05 am, john larkin wrote:
>>>>> On Tue, 17 Mar 2026 22:30:01 +0000, someone
>>>>> <cffbf4deb9142bce48974efc0e64dede@example.com> wrote:
>>>>>
>>>>>> I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB.  One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms?
>>>>>
>>>>> Yes, loadable up-counter with carry chain.
>>>>>
>>>>> This would be in an FPGA, so the diagram is just a concept. The
>>>>> reality will be VHDL code. And the FPGA boys use the Wishbone
>>>>> architecture and want the counter to be 32 bits, which is OK with me.
>>>>>
>>>>> We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so
>>>>> I expect we could do a divider in that ballpark.  The T20 is in the
>>>>> *slow* Efinix family.
>>>>>
>>>>> I think the T20 has 18-bit fast carry chains.
>>>>>
>>>>> After the boys code this, the tools can verify timing.
>>>>>
>>>>> FPGAs are great, but there's a cultural gap between people who draw
>>>>> and people who type.
>>>>
>>>> Can't say I've noticed that, but since I can do both, and most of the
>>>> engineers I've hung out with could too, John Larkin may be projecting here.
>>>
>>> Gosh Bill, you are wonderful. You are great at everything.
>>
>> I'm certainly not great at writing VHDL. There's a VHDL text-book on my
>> bookshelf - bought for a project which didn't come off - but the stuff I
>> did type was in a much less powerful language, but powerful enough to
>> get the chip to do what I wanted it to.
>>
>>> What are you designing now?
>>
>> Absolutely nothing. I do fish for work from time to time, but at 83 I'm
>> not an attractive employee.
> 
> Join one of those maker space things, meet some people, offer to help
> for free, see what happens.

I'm active on the committee of NSW branch of the IEEE but I don't know 
of any maker space things in Sydney.

>>> I designed some PLDs, from PALS to PEELS to the antifuse Actel FPGAs,
>>> but it's mostly grunt work, so I give requirements to kids to type the
>>> VHDL for me. I have an ex-physicist doing that for us now.
>>
>> Getting anything to work is mostly grunt work.
>>
>>> What was interesting about the otp Actel parts is that the design was
>>> schematic entry, and it had to be right the first time.
>>
>> One time programmable parts are like that. It's nice to be able simulate
>> the design before you blow the fuses.
> 
> We invented our triggered, phaselocked LC oscillator, which is pretty
> gnarly. We progammed the loop into an Actel and it locked first try.

When you first started talking about it, you'd dug it out of 
Hewlett-Packard Journal article from the 1970's. Triggered oscillators 
for precision timing have always struck me as terrible idea. They were a 
lot less terrible in 1970's when regular oscillators weren't all that 
good either.
> 
> The OTPs are like laying out a PCB: check it hard and get it right. At
> least you can hack a PCB.
> 
>>> Modern FPGA design is like cpu coding: hack it fast and run it and see
>>> what happens and when it doesn't work, fix it.
>>
>> Reprogrammable parts are lot more forgiving. Hacking it fast isn't a
>> great way to design stuff. It too easy to dive down the wrong rabbit
>> hole, and keep digging, when you ought sit back and think it out again.
>>
>> Big software projects have exactly the same problem. Windows is a
>> steaming heap of legacy software.
> 
> Garbage, but continually being repaired.

Not exactly garbage, but they do keep finding and fixing imperfections.
I'm still running Windows 7. My laptop runs Windows 10. I'm not moved to 
try to up-grade, and when I talked to a Microsoft ambassador I happen to 
know he did mention that Windows 10 does like to interrogate an identity 
chip on start up - a chip that my 2011 desk-top computer doesn't have.

-- 
Bill Sloman, Sydney

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Thread

fast divider? john larkin <jl@glen--canyon.com> - 2026-03-15 11:47 -0700
  Re: fast divider? someone <cffbf4deb9142bce48974efc0e64dede@example.com> - 2026-03-17 22:30 +0000
    Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-19 10:05 -0700
      Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-21 16:36 +1100
        Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-21 07:52 -0700
          Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-22 03:00 +1100
            Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-27 11:39 -0700
              Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-28 16:44 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-28 14:38 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-29 15:52 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-29 08:18 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-30 16:42 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-30 08:00 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-31 16:35 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-31 02:40 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-31 22:30 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-31 08:14 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-04-01 15:54 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-04-01 01:06 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-04-02 02:13 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-04-01 09:12 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-04-02 14:41 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-04-02 07:53 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-04-03 02:21 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-04-02 08:57 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-04-03 04:05 +1100
          Re: fast divider? someone <cffbf4deb9142bce48974efc0e64dede@example.com> - 2026-03-26 23:30 +0000
        Re: fast divider? Ross Finlayson <ross.a.finlayson@gmail.com> - 2026-03-21 09:38 -0700
          Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-21 10:29 -0700
            Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-23 23:49 +1100
              Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-23 08:20 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-24 23:04 +1100
                Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-24 05:56 -0700
                Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-25 02:47 +1100

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