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Groups > comp.arch.fpga > #38726
| From | john larkin <jl@glen--canyon.com> |
|---|---|
| Newsgroups | sci.electronics.design, comp.arch.fpga |
| Subject | Re: fast divider? |
| Date | 2026-03-31 08:14 -0700 |
| Organization | A noiseless patient Spider |
| Message-ID | <6honskhhs9lpc60c05dcn16v9pooqe8udp@4ax.com> (permalink) |
| References | (7 earlier) <10qd2fk$26ddd$1@dont-email.me> <gd3lsk15sb7d9ed6jd5kqbus9d057dhqm3@4ax.com> <10qfmfp$326de$2@dont-email.me> <654nskl6fe22od11in65f4mm254qnuc6p5@4ax.com> <10qgb98$39jr5$1@dont-email.me> |
Cross-posted to 2 groups.
On Tue, 31 Mar 2026 22:30:44 +1100, Bill Sloman <bill.sloman@ieee.org> wrote: >On 31/03/2026 8:40 pm, john larkin wrote: >> On Tue, 31 Mar 2026 16:35:49 +1100, Bill Sloman <bill.sloman@ieee.org> >> wrote: >> >>> On 31/03/2026 2:00 am, john larkin wrote: >>>> On Mon, 30 Mar 2026 16:42:12 +1100, Bill Sloman <bill.sloman@ieee.org> >>>> wrote: >>>> >>>>> On 30/03/2026 2:18 am, john larkin wrote: >>>>>> On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>> wrote: >>>>>> >>>>>>> On 29/03/2026 8:38 am, john larkin wrote: >>>>>>>> On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>>> wrote: >>>>>>>> >>>>>>>>> On 28/03/2026 5:39 am, john larkin wrote: >>>>>>>>>> On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>>>>> wrote: >>>>>>>>>> >>>>>>>>>>> On 22/03/2026 1:52 am, john larkin wrote: >>>>>>>>>>>> On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>>>>>>> wrote: >>>>>>>>>>>> >>>>>>>>>>>>> On 20/03/2026 4:05 am, john larkin wrote: >>>>>>>>>>>>>> On Tue, 17 Mar 2026 22:30:01 +0000, someone >>>>>>>>>>>>>> <cffbf4deb9142bce48974efc0e64dede@example.com> wrote: >>>>>>>>>>>>>> >>>>>>>>>>>>>>> I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms? >>>>>>>>>>>>>> >>>>>>>>>>>>>> Yes, loadable up-counter with carry chain. >>>>>>>>>>>>>> >>>>>>>>>>>>>> This would be in an FPGA, so the diagram is just a concept. The >>>>>>>>>>>>>> reality will be VHDL code. And the FPGA boys use the Wishbone >>>>>>>>>>>>>> architecture and want the counter to be 32 bits, which is OK with me. >>>>>>>>>>>>>> >>>>>>>>>>>>>> We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so >>>>>>>>>>>>>> I expect we could do a divider in that ballpark. The T20 is in the >>>>>>>>>>>>>> *slow* Efinix family. >>>>>>>>>>>>>> >>>>>>>>>>>>>> I think the T20 has 18-bit fast carry chains. >>>>>>>>>>>>>> >>>>>>>>>>>>>> After the boys code this, the tools can verify timing. >>>>>>>>>>>>>> >>>>>>>>>>>>>> FPGAs are great, but there's a cultural gap between people who draw >>>>>>>>>>>>>> and people who type. >>>>>>>>>>>>> >>>>>>>>>>>>> Can't say I've noticed that, but since I can do both, and most of the >>>>>>>>>>>>> engineers I've hung out with could too, John Larkin may be projecting here. >>>>>>>>>>>> >>>>>>>>>>>> Gosh Bill, you are wonderful. You are great at everything. >>>>>>>>>>> >>>>>>>>>>> I'm certainly not great at writing VHDL. There's a VHDL text-book on my >>>>>>>>>>> bookshelf - bought for a project which didn't come off - but the stuff I >>>>>>>>>>> did type was in a much less powerful language, but powerful enough to >>>>>>>>>>> get the chip to do what I wanted it to. >>>>>>>>>>> >>>>>>>>>>>> What are you designing now? >>>>>>>>>>> >>>>>>>>>>> Absolutely nothing. I do fish for work from time to time, but at 83 I'm >>>>>>>>>>> not an attractive employee. >>>>>>>>>> >>>>>>>>>> Join one of those maker space things, meet some people, offer to help >>>>>>>>>> for free, see what happens. >>>>>>>>> >>>>>>>>> I'm active on the committee of NSW branch of the IEEE but I don't know >>>>>>>>> of any maker space things in Sydney. >>>>>>>> >>>>>>>> Hey, you could google >>>>>>>> >>>>>>>> maker spaces sydney australia >>>>>>> >>>>>>> https://makerspaces.com.au/nsw/sydney >>>>>>> >>>>>>> So they exist. Leather work and needle work (sewing) are supported. I am >>>>>>> a tolerably competent carpenter so I might fit in. As a route into >>>>>>> advanced electronic design it doesn't look promising. >>>>>> >>>>>> We have some of that handicraft stuff here, but we have a lot of >>>>>> people who want to build things that use electronics, and those people >>>>>> aren't usually very good circuit designers. [1] >>>>>> >>>>>> Some of them are actual startups with an idea and some funding. They >>>>>> go to meetups to pitch their ideas and maybe meet people who could >>>>>> help. >>>>>> >>>>>> Studio 45 near here has an occasional meetup with 500 people, free >>>>>> food and beer. We might sponsor one. >>>>>> >>>>>> We had a cool one at a Rivian facility. I met a photonics consultant >>>>>> and recommended Phil's book. And listened to yet another pitch for AI >>>>>> circuit/pcb design. >>>>>> >>>>>> There's one coming up in a pier on the SF Bay, an ocean >>>>>> instrumentetion outfit. That should be fun. >>>>>> >>>>>> I do one or two meetups per month and meet lots of Young Things. >>>>>> >>>>>> The point is that you could show up, and meet people who need >>>>>> electronics, and see what happens. >>>>> >>>>> If I showed up at the right meetings, I might meet people who needed >>>>> electronics. The odds don't look great. >>>>> >>>>>> Or don't. >>>>> >>>>> That would seem to be the rational choice. >>>> >>>> Exactly. Do nothing. Just post insults on forums all day. >>> >>> I post information. When it doesn't inform people that you are a >>> brilliant circuit designer, you feel insulted, though you should be used >>> to that by now. >>> >>>>>> [1] It's impressive how few people are good at electronic design. >>>>> >>>>> Even more impressive that you seem to think you can make that statement. >>>>> If you don't think that a classical emitter-coupled monostable can work, >>>>> your status as a judge of electronic design quality can't be all that high. >>>> >>>> That circuit can certainly work; it's classic=ancient. But not often >>>> useful in this modern world. I didn't like your version because the >>>> input trigger had to be delicately tuned to fire it, and it really >>>> amplified the input pulse more than it one-shotted. It was Spice tuned >>>> until it appeared to work. >>> >>> Many applications have well-defined trigger pulses. I certainly didn't >>> spend any time "deliberately tuning" the circuit. >>> >>> The trigger pulse has to be big enough and fast enough to turn off the >>> normally-on transistor and push enough current into the timing capacitor >>> to get the one-shot action, and the amplification is incidental to that. >>> >>> You didn't recognise the circuit, couldn't see how it worked, and have >>> been trying to deny this obvious point ever since. >> >> That circuit is in the 1964 GE Transistor Manual (7th edition, $2). >> Transistors used to be expensive so their use was minimized. Nowadays >> they cost about nothing. > >Using a broad-band transistor in a classic circuit can give you a much >shorter pulse. Broad-band transistors aren't all that cheap, and there >aren't as many of them around as there used to be, but it can be a >useful option. > >>> This isn't the kind >>> of comment you like reading, and will claim that you are being insulted. >>> Tough. This isn't some kind of mutual approbation society >>> >>>> There are far better, easier, cheaper, more deliberate ways to make a >>>> fast one-shot these days. >>> >>> Which is to say, to make a one-shot whose action you can understand >> >> I usually design circuits that I understand, but what matters is that >> they work. >> >> With Spice or experiment, one can profitably design a circuit that you >> don't understand. I have a cool new sensor simulator circuit that I >> don't understand. > >You really don't want to. They have a nasty habit of doing something >unexpected at inconvenient moments. That's not a nasty habit, it's a talent that I practice and teach. Given an enormous space of undiscovered ideas, one profits from a method of exploring them in parallel with minimal filtering. But inconvenient to who? Certainly not to me. Inventing things is fun and profitable. It is an interesting question: does one understand then invent, or invent and then understand? Great scientific and practical ideas seem to be mostly invent or discover first, understand after. The Plutonium book is full of examples. John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics
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fast divider? john larkin <jl@glen--canyon.com> - 2026-03-15 11:47 -0700
Re: fast divider? someone <cffbf4deb9142bce48974efc0e64dede@example.com> - 2026-03-17 22:30 +0000
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-19 10:05 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-21 16:36 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-21 07:52 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-22 03:00 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-27 11:39 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-28 16:44 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-28 14:38 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-29 15:52 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-29 08:18 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-30 16:42 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-30 08:00 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-31 16:35 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-31 02:40 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-31 22:30 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-31 08:14 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-04-01 15:54 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-04-01 01:06 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-04-02 02:13 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-04-01 09:12 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-04-02 14:41 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-04-02 07:53 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-04-03 02:21 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-04-02 08:57 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-04-03 04:05 +1100
Re: fast divider? someone <cffbf4deb9142bce48974efc0e64dede@example.com> - 2026-03-26 23:30 +0000
Re: fast divider? Ross Finlayson <ross.a.finlayson@gmail.com> - 2026-03-21 09:38 -0700
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-21 10:29 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-23 23:49 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-23 08:20 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-24 23:04 +1100
Re: fast divider? john larkin <jl@glen--canyon.com> - 2026-03-24 05:56 -0700
Re: fast divider? Bill Sloman <bill.sloman@ieee.org> - 2026-03-25 02:47 +1100
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