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Groups > linux.kernel > #1624438

[PATCH 29/29] clocksource/drivers/fttmr010: Refactor to handle clock

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From: Linus Walleij <linus.walleij@linaro.org>

The plain Faraday FTTMR010 timer needs a clock to figure out its
tick rate, and the gemini reads it directly from the system
controller set-up. Split the init function and add two paths for
the two compatible-strings. We only support clocking using PCLK
because of lack of documentation on how EXTCLK works.

The Gemini still works like before, but we can also support a
generic, clock-based version.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
 drivers/clocksource/timer-fttmr010.c | 119 +++++++++++++++++++++--------------
 1 file changed, 73 insertions(+), 46 deletions(-)

diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c
index e37ec3d..b4a6f1e 100644
--- a/drivers/clocksource/timer-fttmr010.c
+++ b/drivers/clocksource/timer-fttmr010.c
@@ -16,17 +16,7 @@
 #include <linux/clockchips.h>
 #include <linux/clocksource.h>
 #include <linux/sched_clock.h>
-
-/*
- * Relevant registers in the global syscon
- */
-#define GLOBAL_STATUS		0x04
-#define CPU_AHB_RATIO_MASK	(0x3 << 18)
-#define CPU_AHB_1_1		(0x0 << 18)
-#define CPU_AHB_3_2		(0x1 << 18)
-#define CPU_AHB_24_13		(0x2 << 18)
-#define CPU_AHB_2_1		(0x3 << 18)
-#define REG_TO_AHB_SPEED(reg)	((((reg) >> 15) & 0x7) * 10 + 130)
+#include <linux/clk.h>
 
 /*
  * Register definitions for the timers
@@ -189,23 +179,9 @@ static struct irqaction fttmr010_timer_irq = {
 	.handler	= fttmr010_timer_interrupt,
 };
 
-static int __init gemini_timer_of_init(struct device_node *np)
+static int __init fttmr010_timer_common_init(struct device_node *np)
 {
-	static struct regmap *map;
 	int irq;
-	int ret;
-	u32 val;
-
-	map = syscon_regmap_lookup_by_phandle(np, "syscon");
-	if (IS_ERR(map)) {
-		pr_err("Can't get regmap for syscon handle");
-		return -ENODEV;
-	}
-	ret = regmap_read(map, GLOBAL_STATUS, &val);
-	if (ret) {
-		pr_err("Can't read syscon status register");
-		return -ENXIO;
-	}
 
 	base = of_iomap(np, 0);
 	if (!base) {
@@ -219,26 +195,6 @@ static int __init gemini_timer_of_init(struct device_node *np)
 		return -EINVAL;
 	}
 
-	tick_rate = REG_TO_AHB_SPEED(val) * 1000000;
-	printk(KERN_INFO "Bus: %dMHz", tick_rate / 1000000);
-
-	tick_rate /= 6;		/* APB bus run AHB*(1/6) */
-
-	switch (val & CPU_AHB_RATIO_MASK) {
-	case CPU_AHB_1_1:
-		printk(KERN_CONT "(1/1)\n");
-		break;
-	case CPU_AHB_3_2:
-		printk(KERN_CONT "(3/2)\n");
-		break;
-	case CPU_AHB_24_13:
-		printk(KERN_CONT "(24/13)\n");
-		break;
-	case CPU_AHB_2_1:
-		printk(KERN_CONT "(2/1)\n");
-		break;
-	}
-
 	/*
 	 * Reset the interrupt mask and status
 	 */
@@ -273,4 +229,75 @@ static int __init gemini_timer_of_init(struct device_node *np)
 
 	return 0;
 }
+
+static int __init fttmr010_timer_of_init(struct device_node *np)
+{
+	/*
+	 * These implementations require a clock reference.
+	 * FIXME: we currently only support clocking using PCLK
+	 * and using EXTCLK is not supported in the driver.
+	 */
+	struct clk *clk;
+
+	clk = of_clk_get_by_name(np, "PCLK");
+	if (IS_ERR(clk)) {
+		pr_err("could not get PCLK");
+		return PTR_ERR(clk);
+	}
+	tick_rate = clk_get_rate(clk);
+
+	return fttmr010_timer_common_init(np);
+}
+CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_of_init);
+
+/*
+ * Gemini-specific: relevant registers in the global syscon
+ */
+#define GLOBAL_STATUS		0x04
+#define CPU_AHB_RATIO_MASK	(0x3 << 18)
+#define CPU_AHB_1_1		(0x0 << 18)
+#define CPU_AHB_3_2		(0x1 << 18)
+#define CPU_AHB_24_13		(0x2 << 18)
+#define CPU_AHB_2_1		(0x3 << 18)
+#define REG_TO_AHB_SPEED(reg)	((((reg) >> 15) & 0x7) * 10 + 130)
+
+static int __init gemini_timer_of_init(struct device_node *np)
+{
+	static struct regmap *map;
+	int ret;
+	u32 val;
+
+	map = syscon_regmap_lookup_by_phandle(np, "syscon");
+	if (IS_ERR(map)) {
+		pr_err("Can't get regmap for syscon handle\n");
+		return -ENODEV;
+	}
+	ret = regmap_read(map, GLOBAL_STATUS, &val);
+	if (ret) {
+		pr_err("Can't read syscon status register\n");
+		return -ENXIO;
+	}
+
+	tick_rate = REG_TO_AHB_SPEED(val) * 1000000;
+	pr_info("Bus: %dMHz ", tick_rate / 1000000);
+
+	tick_rate /= 6;		/* APB bus run AHB*(1/6) */
+
+	switch (val & CPU_AHB_RATIO_MASK) {
+	case CPU_AHB_1_1:
+		pr_cont("(1/1)\n");
+		break;
+	case CPU_AHB_3_2:
+		pr_cont("(3/2)\n");
+		break;
+	case CPU_AHB_24_13:
+		pr_cont("(24/13)\n");
+		break;
+	case CPU_AHB_2_1:
+		pr_cont("(2/1)\n");
+		break;
+	}
+
+	return fttmr010_timer_common_init(np);
+}
 CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", gemini_timer_of_init);
-- 
2.7.4

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Thread

[GIT PULL] timers changes for 4.12 Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 18/29] arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 22/29] dt-bindings: Clarify compatible property for rockchip timers Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
    Re: [PATCH 22/29] dt-bindings: Clarify compatible property for  rockchip timers Rob Herring <robh@kernel.org> - 2017-04-20 16:20 +0200
  [PATCH 07/29] arm64: arch_timer: Add erratum handler for CPU-specific capability Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 29/29] clocksource/drivers/fttmr010: Refactor to handle clock Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 11/29] arm64: arch_timer: Make workaround methods optional Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 04/29] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 13/29] arm64: arch_timer: Move clocksource_counter and co around Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 27/29] clocksource: Augment bindings for Faraday timer Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 01/29] arm64: Allow checking of a CPU-local erratum Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
    [PATCH 23/29] ARM: dts: rockchip: Update compatible property for rk322x timer Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
    [PATCH 05/29] arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921 Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 02/29] arm64: Add CNTVCT_EL0 trap handler Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 17/29] arm64: arch_timer: Allow erratum matching with ACPI OEM information Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 08/29] arm64: arch_timer: Move arch_timer_reg_read/write around Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 15/29] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 03/29] arm64: Define Cortex-A73 MIDR Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 10/29] arm64: arch_timer: Rework the set_next_event workarounds Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 26/29] ARM: dts: rockchip: disable arm-global-timer for rk3188 Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 25/29] ARM: dts: rockchip: Add timer entries to rk3188 SoC Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 09/29] arm64: arch_timer: Get rid of erratum_workaround_set_sne Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 21/29] clocksource: Add missing line break to error messages Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
      Re: [PATCH 21/29] clocksource: Add missing line break to error  messages Uwe Kleine-König          <u.kleine-koenig@pengutronix.de> - 2017-04-24 09:50 +0200
    [PATCH 19/29] clocksource/drivers/orion: Read clock rate once Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200

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