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[PATCH 15/29] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled

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From: Marc Zyngier <marc.zyngier@arm.com>

Userspace being allowed to use read CNTVCT_EL0 anytime (and not
only in the VDSO), we need to enable trapping whenever a cntvct
workaround is enabled on a given CPU.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 drivers/clocksource/arm_arch_timer.c | 45 +++++++++++++++++++++++++-----------
 1 file changed, 32 insertions(+), 13 deletions(-)

diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 5c114da..f8adea2 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -83,6 +83,7 @@ static enum ppi_nr arch_timer_uses_ppi = VIRT_PPI;
 static bool arch_timer_c3stop;
 static bool arch_timer_mem_use_virtual;
 static bool arch_counter_suspend_stop;
+static bool vdso_default = true;
 
 static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
 
@@ -383,6 +384,17 @@ void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa
 	}
 
 	static_branch_enable(&arch_timer_read_ool_enabled);
+
+	/*
+	 * Don't use the vdso fastpath if errata require using the
+	 * out-of-line counter accessor. We may change our mind pretty
+	 * late in the game (with a per-CPU erratum, for example), so
+	 * change both the default value and the vdso itself.
+	 */
+	if (wa->read_cntvct_el0) {
+		clocksource_counter.archdata.vdso_direct = false;
+		vdso_default = false;
+	}
 }
 
 static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
@@ -443,11 +455,19 @@ static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type t
 	__val;								\
 })
 
+static bool arch_timer_this_cpu_has_cntvct_wa(void)
+{
+	const struct arch_timer_erratum_workaround *wa;
+
+	wa = __this_cpu_read(timer_unstable_counter_workaround);
+	return wa && wa->read_cntvct_el0;
+}
 #else
 #define arch_timer_check_ool_workaround(t,a)		do { } while(0)
 #define erratum_set_next_event_tval_virt(...)		({BUG(); 0;})
 #define erratum_set_next_event_tval_phys(...)		({BUG(); 0;})
 #define erratum_handler(fn, r, ...)			({false;})
+#define arch_timer_this_cpu_has_cntvct_wa()		({false;})
 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
 
 static __always_inline irqreturn_t timer_handler(const int access,
@@ -660,15 +680,23 @@ static void arch_counter_set_user_access(void)
 {
 	u32 cntkctl = arch_timer_get_cntkctl();
 
-	/* Disable user access to the timers and the physical counter */
+	/* Disable user access to the timers and both counters */
 	/* Also disable virtual event stream */
 	cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
 			| ARCH_TIMER_USR_VT_ACCESS_EN
+		        | ARCH_TIMER_USR_VCT_ACCESS_EN
 			| ARCH_TIMER_VIRT_EVT_EN
 			| ARCH_TIMER_USR_PCT_ACCESS_EN);
 
-	/* Enable user access to the virtual counter */
-	cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
+	/*
+	 * Enable user access to the virtual counter if it doesn't
+	 * need to be workaround. The vdso may have been already
+	 * disabled though.
+	 */
+	if (arch_timer_this_cpu_has_cntvct_wa())
+		pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
+	else
+		cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
 
 	arch_timer_set_cntkctl(cntkctl);
 }
@@ -791,16 +819,7 @@ static void __init arch_counter_register(unsigned type)
 		else
 			arch_timer_read_counter = arch_counter_get_cntpct;
 
-		clocksource_counter.archdata.vdso_direct = true;
-
-#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
-		/*
-		 * Don't use the vdso fastpath if errata require using
-		 * the out-of-line counter accessor.
-		 */
-		if (static_branch_unlikely(&arch_timer_read_ool_enabled))
-			clocksource_counter.archdata.vdso_direct = false;
-#endif
+		clocksource_counter.archdata.vdso_direct = vdso_default;
 	} else {
 		arch_timer_read_counter = arch_counter_get_cntvct_mem;
 	}
-- 
2.7.4

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[GIT PULL] timers changes for 4.12 Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 18/29] arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 22/29] dt-bindings: Clarify compatible property for rockchip timers Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
    Re: [PATCH 22/29] dt-bindings: Clarify compatible property for  rockchip timers Rob Herring <robh@kernel.org> - 2017-04-20 16:20 +0200
  [PATCH 07/29] arm64: arch_timer: Add erratum handler for CPU-specific capability Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 29/29] clocksource/drivers/fttmr010: Refactor to handle clock Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 11/29] arm64: arch_timer: Make workaround methods optional Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 04/29] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 13/29] arm64: arch_timer: Move clocksource_counter and co around Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 27/29] clocksource: Augment bindings for Faraday timer Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
  [PATCH 01/29] arm64: Allow checking of a CPU-local erratum Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
    [PATCH 23/29] ARM: dts: rockchip: Update compatible property for rk322x timer Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:30 +0200
    [PATCH 05/29] arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921 Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 02/29] arm64: Add CNTVCT_EL0 trap handler Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 17/29] arm64: arch_timer: Allow erratum matching with ACPI OEM information Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 08/29] arm64: arch_timer: Move arch_timer_reg_read/write around Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 15/29] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 03/29] arm64: Define Cortex-A73 MIDR Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 10/29] arm64: arch_timer: Rework the set_next_event workarounds Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 26/29] ARM: dts: rockchip: disable arm-global-timer for rk3188 Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 25/29] ARM: dts: rockchip: Add timer entries to rk3188 SoC Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 09/29] arm64: arch_timer: Get rid of erratum_workaround_set_sne Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
    [PATCH 21/29] clocksource: Add missing line break to error messages Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200
      Re: [PATCH 21/29] clocksource: Add missing line break to error  messages Uwe Kleine-König          <u.kleine-koenig@pengutronix.de> - 2017-04-24 09:50 +0200
    [PATCH 19/29] clocksource/drivers/orion: Read clock rate once Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-04-16 22:40 +0200

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