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Groups > linux.kernel > #1594760
| From | Ricardo Neri <ricardo.neri-calderon@linux.intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [v6 PATCH 16/21] x86/cpufeature: Add User-Mode Instruction Prevention definitions |
| Date | 2017-03-08 01:40 +0100 |
| Message-ID | <tixO2-76a-35@gated-at.bofh.it> (permalink) |
| References | <tixO1-76a-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
User-Mode Instruction Prevention is a security feature present in new Intel processors that, when set, prevents the execution of a subset of instructions if such instructions are executed in user mode (CPL > 0). Attempting to execute such instructions causes a general protection exception. The subset of instructions comprises: * SGDT - Store Global Descriptor Table * SIDT - Store Interrupt Descriptor Table * SLDT - Store Local Descriptor Table * SMSW - Store Machine Status Word * STR - Store Task Register This feature is also added to the list of disabled-features to allow a cleaner handling of build-time configuration. Cc: Andy Lutomirski <luto@kernel.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Borislav Petkov <bp@suse.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Chen Yucong <slaoub@gmail.com> Cc: Chris Metcalf <cmetcalf@mellanox.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Huang Rui <ray.huang@amd.com> Cc: Jiri Slaby <jslaby@suse.cz> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi V. Shankar <ravi.v.shankar@intel.com> Cc: Shuah Khan <shuah@kernel.org> Cc: Vlastimil Babka <vbabka@suse.cz> Cc: Tony Luck <tony.luck@intel.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Liang Z. Li <liang.z.li@intel.com> Cc: Alexandre Julliard <julliard@winehq.org> Cc: Stas Sergeev <stsp@list.ru> Cc: x86@kernel.org Cc: linux-msdos@vger.kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com> --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/disabled-features.h | 8 +++++++- arch/x86/include/uapi/asm/processor-flags.h | 2 ++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 4e77723..0739f1e 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -286,6 +286,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ +#define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */ #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index 85599ad..4707445 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -16,6 +16,12 @@ # define DISABLE_MPX (1<<(X86_FEATURE_MPX & 31)) #endif +#ifdef CONFIG_X86_INTEL_UMIP +# define DISABLE_UMIP 0 +#else +# define DISABLE_UMIP (1<<(X86_FEATURE_UMIP & 31)) +#endif + #ifdef CONFIG_X86_64 # define DISABLE_VME (1<<(X86_FEATURE_VME & 31)) # define DISABLE_K6_MTRR (1<<(X86_FEATURE_K6_MTRR & 31)) @@ -55,7 +61,7 @@ #define DISABLED_MASK13 0 #define DISABLED_MASK14 0 #define DISABLED_MASK15 0 -#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE) +#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_UMIP) #define DISABLED_MASK17 0 #define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h index 567de50..d2c2af8 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -104,6 +104,8 @@ #define X86_CR4_OSFXSR _BITUL(X86_CR4_OSFXSR_BIT) #define X86_CR4_OSXMMEXCPT_BIT 10 /* enable unmasked SSE exceptions */ #define X86_CR4_OSXMMEXCPT _BITUL(X86_CR4_OSXMMEXCPT_BIT) +#define X86_CR4_UMIP_BIT 11 /* enable UMIP support */ +#define X86_CR4_UMIP _BITUL(X86_CR4_UMIP_BIT) #define X86_CR4_VMXE_BIT 13 /* enable VMX virtualization */ #define X86_CR4_VMXE _BITUL(X86_CR4_VMXE_BIT) #define X86_CR4_SMXE_BIT 14 /* enable safer mode (TXT) */ -- 2.9.3
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[v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:40 +0100
[v6 PATCH 09/21] x86/insn-eval: Add functions to get default operand and address sizes Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:40 +0100
[v6 PATCH 03/21] x86/mpx: Do not use R/EBP as base in the SIB byte with Mod = 0 Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:40 +0100
[v6 PATCH 08/21] x86/insn-eval: Add utility function to get segment descriptor base address Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:40 +0100
[v6 PATCH 15/21] x86/mm: Relocate page fault error codes to traps.h Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:40 +0100
Re: [v6 PATCH 15/21] x86/mm: Relocate page fault error codes to traps.h Andy Lutomirski <luto@amacapital.net> - 2017-03-08 17:10 +0100
[v6 PATCH 11/21] insn/eval: Incorporate segment base in address computation Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:40 +0100
[v6 PATCH 16/21] x86/cpufeature: Add User-Mode Instruction Prevention definitions Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:40 +0100
[v6 PATCH 21/21] selftests/x86: Add tests for User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:40 +0100
Re: [v6 PATCH 21/21] selftests/x86: Add tests for User-Mode Instruction Prevention Andy Lutomirski <luto@amacapital.net> - 2017-03-08 17:30 +0100
Re: [v6 PATCH 21/21] selftests/x86: Add tests for User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-11 00:40 +0100
[v6 PATCH 01/21] x86/mpx: Use signed variables to compute effective addresses Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:40 +0100
[v6 PATCH 20/21] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:50 +0100
[v6 PATCH 13/21] x86/insn-eval: Add support to resolve 16-bit addressing encodings Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:50 +0100
[v6 PATCH 17/21] x86: Add emulation code for UMIP instructions Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:50 +0100
[v6 PATCH 05/21] x86/insn-eval: Add utility functions to get register offsets Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:50 +0100
[v6 PATCH 12/21] x86/insn: Support both signed 32-bit and 64-bit effective addresses Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:50 +0100
[v6 PATCH 07/21] x86/insn-eval: Add utility function to get segment descriptor Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:50 +0100
[v6 PATCH 18/21] x86/umip: Force a page fault when unable to copy emulated result to user Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:50 +0100
[v6 PATCH 14/21] x86/insn-eval: Add wrapper function for 16-bit and 32-bit address encodings Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 01:50 +0100
[v6 PATCH 06/21] x86/insn-eval: Add utility functions to get segment selector Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 02:00 +0100
[v6 PATCH 02/21] x86/mpx: Do not use SIB index if index points to R/ESP Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 02:00 +0100
[v6 PATCH 19/21] x86/traps: Fixup general protection faults caused by UMIP Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 02:00 +0100
Re: [v6 PATCH 19/21] x86/traps: Fixup general protection faults caused by UMIP Andy Lutomirski <luto@amacapital.net> - 2017-03-08 17:00 +0100
[v6 PATCH 10/21] x86/insn-eval: Do not use R/EBP as base if mod in ModRM is zero Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 02:10 +0100
[v6 PATCH 04/21] x86/mpx, x86/insn: Relocate insn util functions to a new insn-kernel Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-08 04:50 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Stas Sergeev <stsp@list.ru> - 2017-03-08 15:30 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Stas Sergeev <stsp@list.ru> - 2017-03-08 18:00 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-09 02:20 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Stas Sergeev <stsp@list.ru> - 2017-03-09 23:10 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Andy Lutomirski <luto@kernel.org> - 2017-03-10 03:50 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Stas Sergeev <stsp@list.ru> - 2017-03-10 22:00 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Andy Lutomirski <luto@amacapital.net> - 2017-03-10 22:10 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Stas Sergeev <stsp@list.ru> - 2017-03-10 22:40 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Andy Lutomirski <luto@amacapital.net> - 2017-03-08 18:20 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-09 02:20 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Stas Sergeev <stsp@list.ru> - 2017-03-09 23:20 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Andy Lutomirski <luto@amacapital.net> - 2017-03-10 03:50 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Stas Sergeev <stsp@list.ru> - 2017-03-10 12:40 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Andy Lutomirski <luto@amacapital.net> - 2017-03-10 15:20 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-11 02:30 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-11 01:10 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-11 01:00 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Stas Sergeev <stsp@list.ru> - 2017-03-08 23:30 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Andy Lutomirski <luto@amacapital.net> - 2017-03-08 23:50 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-09 02:50 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Stas Sergeev <stsp@list.ru> - 2017-03-10 02:30 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-11 00:50 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Stas Sergeev <stsp@list.ru> - 2017-03-11 01:00 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-03-11 01:20 +0100
Re: [v6 PATCH 00/21] x86: Enable User-Mode Instruction Prevention Andy Lutomirski <luto@amacapital.net> - 2017-03-08 17:20 +0100
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