Well thats good, co-location, onto the same processor die (Re: GPU Cache Hierarchy: Understanding L1, L2, and VRAM (Was: L1,..,Ln caches are located on the CPU AND on the GPU)

From	Mild Shock <janburse@fastmail.fm>
Newsgroups	sci.logic, comp.lang.prolog, sci.physics
Subject	Well thats good, co-location, onto the same processor die (Re: GPU Cache Hierarchy: Understanding L1, L2, and VRAM (Was: L1,..,Ln caches are located on the CPU AND on the GPU)
Date	2026-07-20 22:02 +0200
Message-ID	<113lut1$4dca$2@solani.org> (permalink)
References	(1 earlier) <113i6to$1r2p$2@solani.org> <113kfgk$3b4e$2@solani.org> <113l29d$3oqg$2@solani.org> <113lm87$4rml$2@solani.org> <113lmja$4s3m$1@solani.org>

Cross-posted to 3 groups.

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Hi,

 > That's too located close to the same cpu, idiot.

Yes, colocating a CPU and GPU onto the same
processor die or package provides massive b
enefits, primarily by eliminating the latency
and bandwidth bottlenecks of moving data
across a motherboard.

Individual L1 Caches: Yes, the CPU cores and
the GPU compute units (Streaming Multiprocessors /
Compute Units) still maintain private,
individual L1 caches.

The "Colocation" Benefit: In traditional
setups (a separate CPU and GPU on PCIe slots),
data must be copied from system RAM to the
GPU's VRAM. When a CPU and GPU are colocated
(like in Apple Silicon, AMD APUs, or Intel
processors), they share a Unified Memory
Architecture (UMA). Both processors can read
and write to the exact same physical memory
pool without redundant data copying

Shared Last-Level Cache: While the L1 caches
remain separate, colocated architectures
often share a high-capacity Last-Level
Cache (L2 or L3). This allows the CPU and
GPU to quickly pass data back and forth
locally on the chip.

Bye

Mild Shock schrieb:
> Hi,
> 
> Just read something for once you alcoholic:
> 
> GPU Cache Hierarchy: Understanding L1, L2, and VRAM
> https://charlesgrassi.dev/blog/gpu-cache-hierarchy/
> 
> Measuring Cache Efficiency
> 
> GPU profilers like NVIDIA Nsight, AMD Radeon
> GPU Profiler, and RenderDoc expose cache hit
> rates and memory throughput. Key metrics to watch:
> 
> - L1 Hit Rate: Should be >80% for well-optimized
>      shaders. Below 60% indicates access pattern problems.
> - L2 Hit Rate: Measures working set fit.
>      Below 70% suggests texture thrashing or too many unique textures.
> - Texture Memory Throughput: Compare to theoretical
>      max. Low throughput with high latency = cache misses.
> - Memory-bound vs Compute-bound: If memory is the
>      bottleneck, cache optimization has highest impact.
> 
> If the GPU is a discrete GPU, it has VRAM,
> If the GPU is an accelerator processing unit (APU),
> it shares the system memory with the CPU.
> 
> In the APU scenrio often advanced unified memory
> is used, which can be multi channel for example.
> The high L1 and L2 hit rate for shaders, translates
> 
> also to pi-WAM. Which shows, in the example I used,
> a quite good GPU saturation, less memory bound and
> more compute bound. I have compute these figures already.
> 
> Bye
> 
> Mild Shock schrieb:
>>
>> Hi,
>>
>> You are a moron right? Modern GPU has its
>> own L1,..,Ln caches. RTFM ASAP you brain
>> amputated vodka alcoholic.
>>
>> Russian Hardbass - Crazy Dance
>> https://www.youtube.com/watch?v=6OoglRuT0jY
>>
>> Bye
>>
>> Jeiker Makulov schrieb:
>>  > Mild Shock wrote:
>>  >
>>  >> Yes of course, Micro Penis will know. Nothing, LoL But here we 
>> find how
>>  >> village idiot Micro Penis is.
>>  >> The Cache Identity Crisis by Micro Penis:
>>  >>
>>  >> Claiming that L1/L2/L3 caches and core topology are "embedded cpu
>>  >> registers area,
>>  >> it has nothing to do with the ram." That is a brilliant piece of
>>  >> hardware fiction.
>>  >>
>>  >> Caches are SRAM acting as a hierarchical
>>  >
>>  > imbecile, formatting code like that puts you in prison in normal
>>  > countries. You are using entire lines for single chars, ie  "}" etc,
>>  > imbecile.
>>  >
>>  > also, fucking lying illiterate imbecile
>>  >
>>  > L1, L2, and L3 caches are located on the CPU, not in the system 
>> RAM. They
>>  > form a high-speed memory hierarchy embedded directly within or 
>> immediately
>>  > adjacent to the processor cores to minimize data access latency.
>>  >
>>
>

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        GPU Cache Hierarchy: Understanding L1, L2, and VRAM (Was: L1,..,Ln caches are located on the CPU AND on the GPU) Mild Shock <janburse@fastmail.fm> - 2026-07-20 19:40 +0200
          Well thats good, co-location, onto the same processor die (Re: GPU Cache Hierarchy: Understanding L1, L2, and VRAM (Was: L1,..,Ln caches are located on the CPU AND on the GPU) Mild Shock <janburse@fastmail.fm> - 2026-07-20 22:02 +0200
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