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Groups > sci.physics > #896334
| From | Mild Shock <janburse@fastmail.fm> |
|---|---|
| Newsgroups | sci.logic, comp.lang.prolog, sci.physics |
| Subject | The large memory tax: ECC RAM (Re: Just RTFM the RDNA 3.5 specs! [GPU Cache Lines]) |
| Date | 2026-07-20 14:23 +0200 |
| Message-ID | <113l400$3q5j$2@solani.org> (permalink) |
| References | <10seeh6$rsl4$2@solani.org> <113i6to$1r2p$2@solani.org> <113kfgk$3b4e$2@solani.org> <113l29d$3oqg$2@solani.org> <113l387$3plc$2@solani.org> |
Cross-posted to 3 groups.
Hi,
in high-stakes environments—whether
it's enterprise servers running mission-
critical transactions or heavy parallel
compute clusters crunching massive datasets.
At scale, a "soft error" (a bit randomly
flipping from 0 to 1) isn't a rare anomaly;
it is a statistical certainty.
ECC requires extra bits per data word
(e.g., a 72-bit bus for 64 bits of data) a
nd a small computational cycle overhead to
compute and check parity bits on every access.
instead of instantly crashing the entire
system, modern processors use data poisoning.
The memory controller or cache logic stamps a
"poison bit" or signature onto that specific
cache line and propagates it along with
the corrupted data.
Bye
Mild Shock schrieb:
> Hi,
>
> If you don't know how GPU caches work.
> Just RTFM the RDNA 3.5 specs! They have
> some explanations in the docs, what jobs
>
> the GPU cache lines do, in relation to
> what instructions:
>
> Abbreviation for ‘Read The Fucking Manual’.
> http://www.catb.org/esr/jargon/html/R/RTFM.html
>
> Here some RDNA 4.0 specs (smaller GPUs):
>
> "RDNA4" Instruction Set Architecture
> Reference Guide - 7-April-2025
> https://docs.amd.com/v/u/en-US/rdna4-instruction-set-architecture
>
> Here some CDNA 4.0 specs (bigger GPUs):
>
> CDNA4 Instruction Set Architecture
> Reference Guide - 5-August-2025
> https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna4-instruction-set-architecture.pdf
>
>
> Bye
>
> But the difference between CDNA GPUs and
> RDNA GPUs seems not to be that big, at least
> in 2025:
>
> Commitment to High-Performance
> Computing in the Age of AI
> https://docs.amd.com/v/u/en-US/precision-at-scale-amd-whitepaper
>
> While the Copilot+ threshold is 45 TFLOPs,
> a MI355X, Datacenter, rack-mounted, liquid cooling,
> has surely more memory, but only 157 TFLOPS.
>
> And RTX 5090, Desktop, 600W+ TDP, massive cooling,
> has also only 100 TFLOPS. So it looks these
> Copilot+ AI Laptops are pretty swell, arent they?
>
> Mild Shock schrieb:
>> Hi,
>>
>> > completely nonsense. Not even correct grammatically
>>
>> Yes of course, Micro Penis will know. Nothing, LoL
>> But here we find how village idiot Micro Penis is.
>> The Cache Identity Crisis by Micro Penis:
>>
>> Claiming that L1/L2/L3 caches and core
>> topology are "embedded cpu registers area,
>> it has nothing to do with the ram." That is
>> a brilliant piece of hardware fiction.
>>
>> Caches are SRAM acting as a hierarchical
>> staging ground for and backed by system
>> or device RAM, not an alternate dimension
>> divorced from memory entirely.
>>
>> And calling cache hierarchies "registers"
>> is like confusing a warehouse parking lot
>> with the glove compartment of a single car.
>> Never heard of the crossbar in AMD GPUs?
>>
>> LoL
>>
>> Bye
>>
>> Obelin Baisaroff schrieb:
>> > Ross Finlayson wrote:
>> >
>> >> access to memory, has that these days with
>> >> L1/L2/L3 caches and the proximity and affinity
>> >> in the topology of the cores and
>> >
>> > those are embedded cpu registers area, it has
>> > nothing to do with the ram. Works by higher
>> > clocks compared, but merely useless in AI.
>> >
>>
>>
>> Romelio Balakhonsky schrieb:
>> > Mild Shock wrote:
>> >
>> >> me about lazySet() in Java. But I went with set():
>> >>
>> >> private static boolean enqueue(Queue q, Object data) {
>> >> int pos = q.enqueuePos.get();
>> >> for (; ; ) {
>> >> int index = pos & q.bufferMask; int seq =
>> >> q.sequences.get(index);
>> >> int dif = seq - pos;
>> >> if (dif == 0) {
>> >> if (q.enqueuePos.compareAndSet(pos, pos + 1)) {
>> >> q.data[index] = data; q.sequences.set(index,
>> pos +
>> >> 1);
>> >> return true;
>> >> }
>> >> pos = q.enqueuePos.get();
>> >> } else if (dif < 0) {
>> >> return false;
>> >> } else {
>> >> pos = q.enqueuePos.get();
>> >> }
>> >> }
>> >> }
>> >>
>> >> The above version seems to be more suitable for my purpose, since it
>> >> allows polling, it basically implements offer(). While the
>> >
>> > completely nonsense. Not even correct grammatically
>> >
>>
>
Back to sci.physics | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread
I'm a spinner, I'm a sinner [Dmitry Vyukov for pi-WAM] (Re: Paul Tarau versus Mr. Taskmanager, who would win? [A PDP-11 Humunkulus from 1979] Mild Shock <janburse@fastmail.fm> - 2026-07-19 11:55 +0200
Gemini, DeepSeek, OpenAI all know Dmitriy V'jukov (Re: I'm a spinner, I'm a sinner [Dmitry Vyukov for pi-WAM]) Mild Shock <janburse@fastmail.fm> - 2026-07-20 08:33 +0200
The Cache Identity Crisis by Micro Penis (Re: Gemini, DeepSeek, OpenAI all know Dmitriy V'jukov) Mild Shock <janburse@fastmail.fm> - 2026-07-20 13:54 +0200
Just RTFM the RDNA 3.5 specs! [GPU Cache Lines] (Re: The Cache Identity Crisis by Micro Penis) Mild Shock <janburse@fastmail.fm> - 2026-07-20 14:10 +0200
The large memory tax: ECC RAM (Re: Just RTFM the RDNA 3.5 specs! [GPU Cache Lines]) Mild Shock <janburse@fastmail.fm> - 2026-07-20 14:23 +0200
Re: Just RTFM the RDNA 3.5 specs! [GPU Cache Lines] (Re: The Cache Identity Crisis by Micro Penis) Ross Finlayson <ross.a.finlayson@gmail.com> - 2026-07-20 12:26 -0700
Re: Just RTFM the RDNA 3.5 specs! [GPU Cache Lines] (Re: The Cache Identity Crisis by Micro Penis) R Kym Horsell <kymhorsell@gmail.com> - 2026-07-20 22:20 +0000
Friendly Reminder: GPU 10x more performant than CPU (Was: Just RTFM the RDNA 3.5 specs! [GPU Cache Lines]) Mild Shock <janburse@fastmail.fm> - 2026-07-21 00:39 +0200
Breaking the CUDA edge in AI by WebGPU (Was: Friendly Reminder: GPU 10x more performant than CPU) Mild Shock <janburse@fastmail.fm> - 2026-07-21 00:56 +0200
Like WebAssembly before it, WebGPU has "escaped" the browser. (Was: Breaking the CUDA edge in AI by WebGPU) Mild Shock <janburse@fastmail.fm> - 2026-07-21 01:05 +0200
If you are paranoid you can use Falco [Agentic AI] (Re: Like WebAssembly before it, WebGPU has "escaped" the browser.) Mild Shock <janburse@fastmail.fm> - 2026-07-21 22:57 +0200
What would an EMACS guru say [Windows Recall] (Re: If you are paranoid you can use Falco [Agentic AI]) Mild Shock <janburse@fastmail.fm> - 2026-07-21 23:35 +0200
Decide what you critique tiny winy penis (Re: What would an EMACS guru say [Windows Recall]) Mild Shock <janburse@fastmail.fm> - 2026-07-22 08:17 +0200
How confused is tiny winy penis? (Was: Decide what you critique tiny winy penis) Mild Shock <janburse@fastmail.fm> - 2026-07-22 08:28 +0200
Maybe change your hobby, become a dog owner? (Was: How confused is tiny winy penis?) Mild Shock <janburse@fastmail.fm> - 2026-07-22 09:37 +0200
Even dogs know Switzerland != Germany [Syphilis Brain Micro Penis] (Re: Decide what you critique tiny winy penis ) Mild Shock <janburse@fastmail.fm> - 2026-07-22 11:19 +0200
node.js has also Worker isolation , headless (Was: Even dogs know Switzerland != Germany [Syphilis Brain Micro Penis]) Mild Shock <janburse@fastmail.fm> - 2026-07-22 11:29 +0200
Abyss hobby interpretation vs. professional understanding [Keep up with the Kardashians] (Re: node.js has also Worker isolation , headless) Mild Shock <janburse@fastmail.fm> - 2026-07-22 11:38 +0200
Play stupid games, win classic Usenet prizes [CCCP Troll] (Re: Abyss hobby interpretation vs. professional understanding [Keep up with the Kardashians]) Mild Shock <janburse@fastmail.fm> - 2026-07-22 12:16 +0200
Glue Sniffing 5-Year Old Moron [CCCP Troll] (Was: Play stupid games, win classic Usenet prizes [CCCP Troll]) Mild Shock <janburse@fastmail.fm> - 2026-07-22 14:29 +0200
My Swift Go 16 AI has no IMEI, are you nuts? (Re: Even dogs know Switzerland != Germany [Syphilis Brain Micro Penis]) Mild Shock <janburse@fastmail.fm> - 2026-07-22 14:15 +0200
Same nickname and email, could post faster [5 year old moron] (Re: My Swift Go 16 AI has no IMEI, are you nuts? ) Mild Shock <janburse@fastmail.fm> - 2026-07-22 14:25 +0200
I have nothing to hide, you can find me in search.ch (Re: My Swift Go 16 AI has no IMEI, are you nuts?) Mild Shock <janburse@fastmail.fm> - 2026-07-22 14:41 +0200
Where did I confirm German via .ch, you are more than nuts! (Re: I have nothing to hide, you can find me in search.ch) Mild Shock <janburse@fastmail.fm> - 2026-07-22 14:48 +0200
Ask a Ukrainian Neighbour to do Detective [CCCP Troll] (Re: Where did I confirm German via .ch, you are more than nuts! ) Mild Shock <janburse@fastmail.fm> - 2026-07-22 14:51 +0200
Re: Just RTFM the RDNA 3.5 specs! [GPU Cache Lines] (Re: The Cache Identity Crisis by Micro Penis) Ross Finlayson <ross.a.finlayson@gmail.com> - 2026-07-20 21:36 -0700
rossy boy is going paranoid (Was: Just RTFM the RDNA 3.5 specs! [GPU Cache Lines]) Mild Shock <janburse@fastmail.fm> - 2026-07-21 09:01 +0200
Re: rossy boy is going paranoid (Was: Just RTFM the RDNA 3.5 specs! [GPU Cache Lines]) Ross Finlayson <ross.a.finlayson@gmail.com> - 2026-07-21 00:56 -0700
L1,..,Ln caches are located on the CPU AND on the GPU (Was: The Cache Identity Crisis by Micro Penis( Mild Shock <janburse@fastmail.fm> - 2026-07-20 19:35 +0200
GPU Cache Hierarchy: Understanding L1, L2, and VRAM (Was: L1,..,Ln caches are located on the CPU AND on the GPU) Mild Shock <janburse@fastmail.fm> - 2026-07-20 19:40 +0200
Well thats good, co-location, onto the same processor die (Re: GPU Cache Hierarchy: Understanding L1, L2, and VRAM (Was: L1,..,Ln caches are located on the CPU AND on the GPU) Mild Shock <janburse@fastmail.fm> - 2026-07-20 22:02 +0200
Where is micro penis mental error? (Re: Well thats good, co-location, onto the same processor die (Re: GPU Cache Hierarchy: Understanding L1, L2, and VRAM (Was: L1,..,Ln caches are located on the CPU AND on the GPU) Mild Shock <janburse@fastmail.fm> - 2026-07-20 22:07 +0200
I didn't find Futex in WebGPU / WGSL (Re: Gemini, DeepSeek, OpenAI all know Dmitriy V'jukov) Mild Shock <janburse@fastmail.fm> - 2026-07-20 23:26 +0200
There is no imageAtomicAdd in WGSL (Re: I didn't find Futex in WebGPU / WGSL) Mild Shock <janburse@fastmail.fm> - 2026-07-21 00:15 +0200
OpenGL is dead. Apple said bye bye / Wayland Compositor (Re: There is no imageAtomicAdd in WGSL) Mild Shock <janburse@fastmail.fm> - 2026-07-21 00:26 +0200
Flogging a Dead Horse, OpenGL is EOL (Re: There is no imageAtomicAdd in WGSL) Mild Shock <janburse@fastmail.fm> - 2026-07-21 01:39 +0200
imageAtomicAdd trivial, Dmitry Vyukov requires capacity (Re: Flogging a Dead Horse, OpenGL is EOL) Mild Shock <janburse@fastmail.fm> - 2026-07-21 01:40 +0200
capacity = 2^n for some n / systolic system (Re: imageAtomicAdd trivial, Dmitry Vyukov requires capacity) Mild Shock <janburse@fastmail.fm> - 2026-07-21 01:41 +0200
Source of the benchmark for DmitryVyukov (Was: capacity = 2^n for some n / systolic system) Mild Shock <janburse@fastmail.fm> - 2026-07-21 01:44 +0200
Re: There is no imageAtomicAdd in WGSL (Re: I didn't find Futex in WebGPU / WGSL) "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-07-20 16:59 -0700
I never used OpenGL Version 4.2 and later (Was: There is no imageAtomicAdd in WGSL) Mild Shock <janburse@fastmail.fm> - 2026-07-21 08:47 +0200
Because of MIMD you have to reassess algorithms (Re: I never used OpenGL Version 4.2 and later) Mild Shock <janburse@fastmail.fm> - 2026-07-21 09:02 +0200
Why MIMD is interesting for pi-WAM? Mild Shock <janburse@fastmail.fm> - 2026-07-21 09:18 +0200
Re: Because of MIMD you have to reassess algorithms (Re: I never used OpenGL Version 4.2 and later) "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-07-22 13:34 -0700
Do you see the loops, in C code and in Java code? /** Looping **/ (Was: Because of MIMD you have to reassess algorithms) Mild Shock <janburse@fastmail.fm> - 2026-07-23 00:09 +0200
Re: Do you see the loops, in C code and in Java code? /** Looping **/ (Was: Because of MIMD you have to reassess algorithms) Mild Shock <janburse@fastmail.fm> - 2026-07-23 00:53 +0200
Re: Do you see the loops, in C code and in Java code? /** Looping **/ (Was: Because of MIMD you have to reassess algorithms) "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-07-22 18:00 -0700
Re: Do you see the loops, in C code and in Java code? /** Looping **/ (Was: Because of MIMD you have to reassess algorithms) "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-07-22 18:20 -0700
Why do you even need a mpmc queue? [Thunder Kittens] (Was: Do you see the loops, in C code and in Java code? /** Looping **/) Mild Shock <janburse@fastmail.fm> - 2026-07-24 14:44 +0200
What does pi in pi-WAM mean? (Re: Why do you even need a mpmc queue? [Thunder Kittens]) Mild Shock <janburse@fastmail.fm> - 2026-07-24 14:53 +0200
OR-parallelism or AND-parallelism? [MapReduce] (Was: What does pi in pi-WAM mean?) Mild Shock <janburse@fastmail.fm> - 2026-07-24 15:00 +0200
It is all on GitHub , for the 100-th time! (Re: What does pi in pi-WAM mean?) Mild Shock <janburse@fastmail.fm> - 2026-07-24 20:13 +0200
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