Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > sci.electronics.design > #452449 > unrolled thread

bad, better delay circuits

Back to article view | Back to sci.electronics.design

Contents

  bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-18 10:04 -0700
    Re: bad, better delay circuits Winfield Hill <hill@rowland.harvard.edu> - 2017-03-18 12:29 -0700
      Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-18 16:15 -0700
        Re: bad, better delay circuits Winfield Hill <hill@rowland.harvard.edu> - 2017-03-18 19:08 -0700
    Re: bad, better delay circuits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-18 17:02 -0500
      Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-18 16:25 -0700
        Re: bad, better delay circuits rickman <gnuarm@gmail.com> - 2017-03-18 19:40 -0400
          Re: bad, better delay circuits dagmargoodboat@yahoo.com - 2017-03-19 10:42 -0700
            Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-19 15:37 -0700
              Re: bad, better delay circuits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-19 22:24 -0500
                Re: bad, better delay circuits dagmargoodboat@yahoo.com - 2017-03-20 08:58 -0700
                  Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-20 09:42 -0700
                    Re: bad, better delay circuits Robert Baer <robertbaer@localnet.com> - 2017-03-20 23:55 -0800
                  Re: bad, better delay circuits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-21 00:46 -0500
                Re: bad, better delay circuits bill.sloman@ieee.org - 2017-03-21 22:54 -0700
                  Re: bad, better delay circuits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-22 02:10 -0500
            Re: bad, better delay circuits rickman <gnuarm@gmail.com> - 2017-03-19 18:47 -0400
              Re: bad, better delay circuits Clifford Heath <no.spam@please.net> - 2017-03-20 09:55 +1100
                Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-19 16:12 -0700
        Re: bad, better delay circuits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-19 10:32 -0500
    Re: bad, better delay circuits Clifford Heath <no.spam@please.net> - 2017-03-19 13:36 +1100
      Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-18 19:44 -0700
        Re: bad, better delay circuits Clifford Heath <no.spam@please.net> - 2017-03-19 15:58 +1100
          Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-19 15:43 -0700
            Re: bad, better delay circuits Winfield Hill <hill@rowland.harvard.edu> - 2017-03-19 17:54 -0700
              Re: bad, better delay circuits Clifford Heath <no.spam@please.net> - 2017-03-20 12:44 +1100
                Re: bad, better delay circuits Winfield Hill <hill@rowland.harvard.edu> - 2017-03-20 12:22 -0700
                  Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-20 15:49 -0700
    Re: bad, better delay circuits whit3rd <whit3rd@gmail.com> - 2017-03-18 23:51 -0700
      Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-19 08:22 -0700
    Re: bad, better delay circuits George Herold <gherold@teachspin.com> - 2017-03-20 17:55 -0700
    Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-22 08:54 -0700
      Re: bad, better delay circuits JM <dontreplytothis173@gmail.com> - 2017-03-22 16:02 +0000
        Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-22 09:47 -0700
      Re: bad, better delay circuits Winfield Hill <hill@rowland.harvard.edu> - 2017-03-22 10:31 -0700
        Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-22 10:52 -0700

Page 1 of 2  [1] 2  Next page →

#452449 — bad, better delay circuits

We want to trim the rising edge times of some pulses. The obvious
circuit is a current source + capacitor linear ramp followed by a
comparator.

The first circuit here was the initial idea, seems simple, until I
started thinking harder.

https://dl.dropboxusercontent.com/u/53724080/Circuits/Timing/Delay_Bad_Good.JPG

BSS123 is about the best compromise between capacitance and ON
resistance, and we have it. The two problems here are

the g-d capacitance of Q1 shoots an ugly negative spike into C1 at
ramp start and

the drain capacitance of Q2 is nonlinear, which is maybe OK, but the
drain voltage can wander all over the place. That modulates the ramp
slope, and the body diode could conduct at ramp discharge time. Fixes
for that are variations of ugly.

E-Phemts would be better than mosfets, but that would multiply the
parts cost by 5x or so. Open-drain cmos gates could be interesting,
but we don't have any in stock


The second circuit looks better. The mux switches in C2, or keeps it
grounded. These "bus switch" parts are actually killer analog
multiplexers at a fraction of the price of things sold as analog
mux's.

The comparator is of course an LVDS line receiver, another example of
using a part off-label and saving a bunch of dollars and nanoseconds.

Another bus switch could be used to discharge the cap, instead of the
diode, but sadly their control-input delays are high. That's the
pattern in mux's: fast signal path, slow switching.




-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics 

[toc] | [next] | [standalone]

#452475

John Larkin wrote...
>
> The second circuit looks better. 

 I'm using diodes to reset 22pF caps for some
 variable nanosecond-delay circuits.  Variable
 pullup, 220-ohm plus 1k pot.  Works well, but
 the issue is what diode?  Need a relatively
 high-current capability for rapid cycling, but
 a moderately low capacitance across the 22pF.
 Ended up with SD103AW, accept the added 15pF.
 SD101AW is only 1.5pF, but too wimpy.  Didn't
 find a small compromise Schottky diode.

 What'd you choose?

 In another case, used 74LVC1G125 or 126 to
 discharge the cap, that worked even better.
 Ground logic input, control with OE pin.
 Very speedy discharge and release.  Remote
 time delay adjustment with voltage to LVDS.
https://www.dropbox.com/s/d1axmzcwdl0bvly/3-state-delay-timer.JPG?dl=0


-- 
 Thanks,
    - Win

[toc] | [prev] | [next] | [standalone]

#452495

On 18 Mar 2017 12:29:24 -0700, Winfield Hill
<hill@rowland.harvard.edu> wrote:

>John Larkin wrote...
>>
>> The second circuit looks better. 
>
> I'm using diodes to reset 22pF caps for some
> variable nanosecond-delay circuits.  Variable
> pullup, 220-ohm plus 1k pot.  Works well, but
> the issue is what diode?  Need a relatively
> high-current capability for rapid cycling, but
> a moderately low capacitance across the 22pF.
> Ended up with SD103AW, accept the added 15pF.
> SD101AW is only 1.5pF, but too wimpy.  Didn't
> find a small compromise Schottky diode.
>
> What'd you choose?

My favorite diode, SMS7611 or the near-equivalent BAT15, around 0.3
pF. But the series resistance is relatively high, 10 ohms maybe, so it
won't discharge a big cap fast. There are some lower resistance parts
in the 1-2 pF range, like SMS3922 at 1 pF.

Hey, 10 ohms and 22 pF is 220 ps! A CMOS driver might be over 10 ohms
by itself. Inductance is going to hurt, too (or possibly help... gotta
Spice that one day.)

A lot of diode capacitance makes the cap voltage hop up at the start
of the ramp, too. 15 pF of diode into 22 pF of ramp cap will be a
jackrabbit hop.

You might consider a smaller ramp cap and less current if you use a
smaller diode. Or discharge with a phemt to ground.

>
> In another case, used 74LVC1G125 or 126 to
> discharge the cap, that worked even better.
> Ground logic input, control with OE pin.

That's interesting; we have those. Prop delay is not going to beat a
schottky diode! I'd want to test for charge injection and whatever.

> Very speedy discharge and release.  Remote
> time delay adjustment with voltage to LVDS.
>https://www.dropbox.com/s/d1axmzcwdl0bvly/3-state-delay-timer.JPG?dl=0

What I'm doing is similar, but we might want to switch delay ranges.

You could use my LED current source:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Current_Sources/LED_Isrc_data.JPG

(We have a few other tricks that are too good to post here.)



-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics 

[toc] | [prev] | [next] | [standalone]

#452530

John Larkin wrote...
>
> Winfield Hill wrote:
>>
>> In another case, used 74LVC1G125 or 126 to
>> discharge the cap, that worked even better.
>> Ground logic input, control with OE pin.
>
> That's interesting; we have those.  Prop delay
> is not going to beat a schottky diode! 

 Yes, but very surprisingly-node capacitance.


-- 
 Thanks,
    - Win

[toc] | [prev] | [next] | [standalone]

#452488

I picked up some RUM001L02T2CL that are a hell of a lot smaller 
(electrically) than garden-variety 2N7002 or BSS138.  For that matter, quite 
a bit smaller (physically) too!

The timing edge into 220pF looks blameless.  At 22pF there may be a bit of 
hook, but not enough to matter (<10%?).

The lower drain voltage rating means "logic level" is compatible even with 
modern low voltage logic.

Should be pretty okay at RF too, given the power limitation.

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com


"John Larkin" <jjlarkin@highlandtechnology.com> wrote in message 
news:1roqcclua35sdrn6jduc9q0folr3fg8oqu@4ax.com...
>
>
> We want to trim the rising edge times of some pulses. The obvious
> circuit is a current source + capacitor linear ramp followed by a
> comparator.
>
> The first circuit here was the initial idea, seems simple, until I
> started thinking harder.
>
> https://dl.dropboxusercontent.com/u/53724080/Circuits/Timing/Delay_Bad_Good.JPG
>
> BSS123 is about the best compromise between capacitance and ON
> resistance, and we have it. The two problems here are
>
> the g-d capacitance of Q1 shoots an ugly negative spike into C1 at
> ramp start and
>
> the drain capacitance of Q2 is nonlinear, which is maybe OK, but the
> drain voltage can wander all over the place. That modulates the ramp
> slope, and the body diode could conduct at ramp discharge time. Fixes
> for that are variations of ugly.
>
> E-Phemts would be better than mosfets, but that would multiply the
> parts cost by 5x or so. Open-drain cmos gates could be interesting,
> but we don't have any in stock
>
>
> The second circuit looks better. The mux switches in C2, or keeps it
> grounded. These "bus switch" parts are actually killer analog
> multiplexers at a fraction of the price of things sold as analog
> mux's.
>
> The comparator is of course an LVDS line receiver, another example of
> using a part off-label and saving a bunch of dollars and nanoseconds.
>
> Another bus switch could be used to discharge the cap, instead of the
> diode, but sadly their control-input delays are high. That's the
> pattern in mux's: fast signal path, slow switching.
>
>
>
>
> -- 
>
> John Larkin         Highland Technology, Inc
>
> lunatic fringe electronics
> 

[toc] | [prev] | [next] | [standalone]

#452496

On Sat, 18 Mar 2017 17:02:36 -0500, "Tim Williams"
<tiwill@seventransistorlabs.com> wrote:

>I picked up some RUM001L02T2CL that are a hell of a lot smaller 
>(electrically) than garden-variety 2N7002 or BSS138.  For that matter, quite 
>a bit smaller (physically) too!
>
>The timing edge into 220pF looks blameless.  At 22pF there may be a bit of 
>hook, but not enough to matter (<10%?).
>
>The lower drain voltage rating means "logic level" is compatible even with 
>modern low voltage logic.
>
>Should be pretty okay at RF too, given the power limitation.
>
>Tim

That's a nice part. Crss is only 1.7 pF, and one could reduce the gate
drive to further reduce charge injection into the ramp cap.

2.5 volts into the gate, 1.7 to 100 pf (my cap) is just 40 millivolts
of jump.

It computes to 200 mV with a 22pF cap, but the channel is still
conducting for part of the gate turn-off swing, so it will be even
less. Needs a breadboard or a good Spice model to be sure.


-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics 

[toc] | [prev] | [next] | [standalone]

#452499

On 3/18/2017 7:25 PM, John Larkin wrote:
> On Sat, 18 Mar 2017 17:02:36 -0500, "Tim Williams"
> <tiwill@seventransistorlabs.com> wrote:
>
>> I picked up some RUM001L02T2CL that are a hell of a lot smaller
>> (electrically) than garden-variety 2N7002 or BSS138.  For that matter, quite
>> a bit smaller (physically) too!
>>
>> The timing edge into 220pF looks blameless.  At 22pF there may be a bit of
>> hook, but not enough to matter (<10%?).
>>
>> The lower drain voltage rating means "logic level" is compatible even with
>> modern low voltage logic.
>>
>> Should be pretty okay at RF too, given the power limitation.
>>
>> Tim
>
> That's a nice part. Crss is only 1.7 pF, and one could reduce the gate
> drive to further reduce charge injection into the ramp cap.
>
> 2.5 volts into the gate, 1.7 to 100 pf (my cap) is just 40 millivolts
> of jump.
>
> It computes to 200 mV with a 22pF cap, but the channel is still
> conducting for part of the gate turn-off swing, so it will be even
> less. Needs a breadboard or a good Spice model to be sure.

Here's a circuit you won't need to spice.

        ___                 ___
    ___|      .-----.   ___|   |___
    ---->>----| MCU |---->>----
              '-----'

You can set a delay, a pulse width, active edge or have it count edges 
before emitting a pulse.  Different delays on the rising and falling 
edge is possible.  A wide variety of things can be done and changed on 
the fly.  The clock can be internal with a good accuracy.  The magic of 
digital logic can do so much.

-- 

Rick C

[toc] | [prev] | [next] | [standalone]

#452608

On Saturday, March 18, 2017 at 7:40:03 PM UTC-4, rickman wrote:
> On 3/18/2017 7:25 PM, John Larkin wrote:
> > On Sat, 18 Mar 2017 17:02:36 -0500, "Tim Williams"
> > <tiwill@seventransistorlabs.com> wrote:
> >
> >> I picked up some RUM001L02T2CL that are a hell of a lot smaller
> >> (electrically) than garden-variety 2N7002 or BSS138.  For that matter, quite
> >> a bit smaller (physically) too!
> >>
> >> The timing edge into 220pF looks blameless.  At 22pF there may be a bit of
> >> hook, but not enough to matter (<10%?).
> >>
> >> The lower drain voltage rating means "logic level" is compatible even with
> >> modern low voltage logic.
> >>
> >> Should be pretty okay at RF too, given the power limitation.
> >>
> >> Tim
> >
> > That's a nice part. Crss is only 1.7 pF, and one could reduce the gate
> > drive to further reduce charge injection into the ramp cap.
> >
> > 2.5 volts into the gate, 1.7 to 100 pf (my cap) is just 40 millivolts
> > of jump.
> >
> > It computes to 200 mV with a 22pF cap, but the channel is still
> > conducting for part of the gate turn-off swing, so it will be even
> > less. Needs a breadboard or a good Spice model to be sure.
> 
> Here's a circuit you won't need to spice.
> 
>         ___                 ___
>     ___|      .-----.   ___|   |___
>     ---->>----| MCU |---->>----
>               '-----'
> 
> You can set a delay, a pulse width, active edge or have it count edges 
> before emitting a pulse.  Different delays on the rising and falling 
> edge is possible.  A wide variety of things can be done and changed on 
> the fly.  The clock can be internal with a good accuracy.  The magic of 
> digital logic can do so much.
> 
> -- 
> 
> Rick C

Very nice.  Now give it pS resolution and jitter and you'll be up to where
John was roughly thirty years ago.

Cheers,
James Arthur

[toc] | [prev] | [next] | [standalone]

#452623

On Sun, 19 Mar 2017 10:42:17 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

>On Saturday, March 18, 2017 at 7:40:03 PM UTC-4, rickman wrote:
>> On 3/18/2017 7:25 PM, John Larkin wrote:
>> > On Sat, 18 Mar 2017 17:02:36 -0500, "Tim Williams"
>> > <tiwill@seventransistorlabs.com> wrote:
>> >
>> >> I picked up some RUM001L02T2CL that are a hell of a lot smaller
>> >> (electrically) than garden-variety 2N7002 or BSS138.  For that matter, quite
>> >> a bit smaller (physically) too!
>> >>
>> >> The timing edge into 220pF looks blameless.  At 22pF there may be a bit of
>> >> hook, but not enough to matter (<10%?).
>> >>
>> >> The lower drain voltage rating means "logic level" is compatible even with
>> >> modern low voltage logic.
>> >>
>> >> Should be pretty okay at RF too, given the power limitation.
>> >>
>> >> Tim
>> >
>> > That's a nice part. Crss is only 1.7 pF, and one could reduce the gate
>> > drive to further reduce charge injection into the ramp cap.
>> >
>> > 2.5 volts into the gate, 1.7 to 100 pf (my cap) is just 40 millivolts
>> > of jump.
>> >
>> > It computes to 200 mV with a 22pF cap, but the channel is still
>> > conducting for part of the gate turn-off swing, so it will be even
>> > less. Needs a breadboard or a good Spice model to be sure.
>> 
>> Here's a circuit you won't need to spice.
>> 
>>         ___                 ___
>>     ___|      .-----.   ___|   |___
>>     ---->>----| MCU |---->>----
>>               '-----'
>> 
>> You can set a delay, a pulse width, active edge or have it count edges 
>> before emitting a pulse.  Different delays on the rising and falling 
>> edge is possible.  A wide variety of things can be done and changed on 
>> the fly.  The clock can be internal with a good accuracy.  The magic of 
>> digital logic can do so much.
>> 
>> -- 
>> 
>> Rick C
>
>Very nice.  Now give it pS resolution and jitter and you'll be up to where
>John was roughly thirty years ago.
>
>Cheers,
>James Arthur

A cheap 50 GHz ARM uP might get close.

Actually, some of the latest FPGAs have insane SERDES blocks, things
like 25 GBPS. Some semi-fast timing could be done with them, but power
consumption and cost and jitter would all be bigly.


-- 

John Larkin         Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

[toc] | [prev] | [next] | [standalone]

#452675

"John Larkin" <jjlarkin@highlandtechnology.com> wrote in message 
news:7r1uccltsgahaujd5o5109ibj1adid6kek@4ax.com...
> A cheap 50 GHz ARM uP might get close.
>
> Actually, some of the latest FPGAs have insane SERDES blocks, things
> like 25 GBPS. Some semi-fast timing could be done with them, but power
> consumption and cost and jitter would all be bigly.

To be fair, there are also chips out there designed for high resolution PWM, 
control and DSP applications, and stuff like that.  They have sub-clock 
timing accuracy thanks to tricks like trimmed and compensated delays, and 
DLL/PLL stuff.  The kind of stuff Don Lancaster used to dream about: enough 
processing power, timing accuracy and output hardware to do real time "Magic 
Sinewaves", say for multiphase motor drives.

But I don't know that any exist for delaying external signals (asynchronous 
trigger).  In that case, you would have to trigger on an interrupt, which 
synchronizes everything anyway (but worse again, if the interrupt latency is 
variable).  If it's periodic, you could DLL it, but gee, what a mess...

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com 

[toc] | [prev] | [next] | [standalone]

#452726

On Sunday, March 19, 2017 at 11:24:06 PM UTC-4, Tim Williams wrote:
> "John Larkin" <jjlarkin@highlandtechnology.com> wrote in message 
> news:7r1uccltsgahaujd5o5109ibj1adid6kek@4ax.com...
> > A cheap 50 GHz ARM uP might get close.
> >
> > Actually, some of the latest FPGAs have insane SERDES blocks, things
> > like 25 GBPS. Some semi-fast timing could be done with them, but power
> > consumption and cost and jitter would all be bigly.
> 
> To be fair, there are also chips out there designed for high resolution PWM, 
> control and DSP applications, and stuff like that.  They have sub-clock 
> timing accuracy thanks to tricks like trimmed and compensated delays, and 
> DLL/PLL stuff.  The kind of stuff Don Lancaster used to dream about: enough 
> processing power, timing accuracy and output hardware to do real time "Magic 
> Sinewaves", say for multiphase motor drives.
> 
> But I don't know that any exist for delaying external signals (asynchronous 
> trigger).  In that case, you would have to trigger on an interrupt, which 
> synchronizes everything anyway (but worse again, if the interrupt latency is 
> variable).  If it's periodic, you could DLL it, but gee, what a mess...

John's been doing that stuff for decades.
http://highlandtechnology.com/categories/digital_delay_generators.shtml

Cheers,
James Arthur

[toc] | [prev] | [next] | [standalone]

#452735

On Mon, 20 Mar 2017 08:58:38 -0700 (PDT), dagmargoodboat@yahoo.com
wrote:

>On Sunday, March 19, 2017 at 11:24:06 PM UTC-4, Tim Williams wrote:
>> "John Larkin" <jjlarkin@highlandtechnology.com> wrote in message 
>> news:7r1uccltsgahaujd5o5109ibj1adid6kek@4ax.com...
>> > A cheap 50 GHz ARM uP might get close.
>> >
>> > Actually, some of the latest FPGAs have insane SERDES blocks, things
>> > like 25 GBPS. Some semi-fast timing could be done with them, but power
>> > consumption and cost and jitter would all be bigly.
>> 
>> To be fair, there are also chips out there designed for high resolution PWM, 
>> control and DSP applications, and stuff like that.  They have sub-clock 
>> timing accuracy thanks to tricks like trimmed and compensated delays, and 
>> DLL/PLL stuff.  The kind of stuff Don Lancaster used to dream about: enough 
>> processing power, timing accuracy and output hardware to do real time "Magic 
>> Sinewaves", say for multiphase motor drives.
>> 
>> But I don't know that any exist for delaying external signals (asynchronous 
>> trigger).  In that case, you would have to trigger on an interrupt, which 
>> synchronizes everything anyway (but worse again, if the interrupt latency is 
>> variable).  If it's periodic, you could DLL it, but gee, what a mess...
>
>John's been doing that stuff for decades.
>http://highlandtechnology.com/categories/digital_delay_generators.shtml
>
>Cheers,
>James Arthur

https://en.wikipedia.org/wiki/Digital_delay_generator#Design

I wrote that part. Wiki wouldn't allow me to footnote my company name
unless I made an actual contribution.

I have one other Wikipedia contribution, the curved icicles picture.


-- 

John Larkin         Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

[toc] | [prev] | [next] | [standalone]

#452866

John Larkin wrote:
> On Mon, 20 Mar 2017 08:58:38 -0700 (PDT), dagmargoodboat@yahoo.com
> wrote:
>
>> On Sunday, March 19, 2017 at 11:24:06 PM UTC-4, Tim Williams wrote:
>>> "John Larkin"<jjlarkin@highlandtechnology.com>  wrote in message
>>> news:7r1uccltsgahaujd5o5109ibj1adid6kek@4ax.com...
>>>> A cheap 50 GHz ARM uP might get close.
>>>>
>>>> Actually, some of the latest FPGAs have insane SERDES blocks, things
>>>> like 25 GBPS. Some semi-fast timing could be done with them, but power
>>>> consumption and cost and jitter would all be bigly.
>>>
>>> To be fair, there are also chips out there designed for high resolution PWM,
>>> control and DSP applications, and stuff like that.  They have sub-clock
>>> timing accuracy thanks to tricks like trimmed and compensated delays, and
>>> DLL/PLL stuff.  The kind of stuff Don Lancaster used to dream about: enough
>>> processing power, timing accuracy and output hardware to do real time "Magic
>>> Sinewaves", say for multiphase motor drives.
>>>
>>> But I don't know that any exist for delaying external signals (asynchronous
>>> trigger).  In that case, you would have to trigger on an interrupt, which
>>> synchronizes everything anyway (but worse again, if the interrupt latency is
>>> variable).  If it's periodic, you could DLL it, but gee, what a mess...
>>
>> John's been doing that stuff for decades.
>> http://highlandtechnology.com/categories/digital_delay_generators.shtml
>>
>> Cheers,
>> James Arthur
>
> https://en.wikipedia.org/wiki/Digital_delay_generator#Design
>
> I wrote that part. Wiki wouldn't allow me to footnote my company name
> unless I made an actual contribution.
>
> I have one other Wikipedia contribution, the curved icicles picture.
>
>
   COOL!

[toc] | [prev] | [next] | [standalone]

#452848

<dagmargoodboat@yahoo.com> wrote in message 
news:01107ebe-4a38-495d-9114-8c0bfc785083@googlegroups.com...
> John's been doing that stuff for decades.
> http://highlandtechnology.com/categories/digital_delay_generators.shtml

With an FPGA and some support hardware, yes, absolutely. :)

Doubt you can find an MCU with that inside, though.  (Maybe you could hack 
it with an SoC, if you don't mind that it's also low bandwidth?  But then 
you might be okay with the MHz+ quantization anyway, so who cares.)

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com 

[toc] | [prev] | [next] | [standalone]

#453009

On Monday, March 20, 2017 at 2:24:06 PM UTC+11, Tim Williams wrote:
> "John Larkin" <jjlarkin@highlandtechnology.com> wrote in message 
> news:7r1uccltsgahaujd5o5109ibj1adid6kek@4ax.com...
> > A cheap 50 GHz ARM uP might get close.
> >
> > Actually, some of the latest FPGAs have insane SERDES blocks, things
> > like 25 GBPS. Some semi-fast timing could be done with them, but power
> > consumption and cost and jitter would all be bigly.
> 
> To be fair, there are also chips out there designed for high resolution PWM, 
> control and DSP applications, and stuff like that.  They have sub-clock 
> timing accuracy thanks to tricks like trimmed and compensated delays, and 
> DLL/PLL stuff.  The kind of stuff Don Lancaster used to dream about: enough 
> processing power, timing accuracy and output hardware to do real time "Magic 
> Sinewaves", say for multiphase motor drives.
> 
> But I don't know that any exist for delaying external signals (asynchronous 
> trigger).

<snip>  

https://www.onsemi.com/pub/Collateral/MC100EP196-D.PDF

It has been around - initially as the MC100E196 - for at least twenty years. 
There were similar parts on offer before that, but I don't know of any that stayed in production.

The delay is temperature dependent. When I wanted to use it I figure on measuring the delays every few minutes and picking the one currently closest to the delay I wanted. You could also stick a Peltier junction onto the top of the device and force the junction to remain at a constant temperature (which wouldn't be an entirely trivial exercise since the ambient temperature would influence the MC100EP196 junction temperature through the bottom of the device and you'd have to over-drive the Peltier junction to keep the relevant bit of slicon at the right temperature).

John Larkin may have been doing that kind of stuff for decades, but we put together a system for exactly that job at Cambridge Instruments from 1988 to 1991.

It was working in 1991 but marketing didn't think that we could sell enough of them - it was part of system that would have sold for  about a quarter of a million dollars per unit - to cover the cost of getting it into full production.

As an asynchronous system, you could have any delay you wanted from about 40nsec up to about 10msec in 10psec steps.

It was intended to be used on stuff that did repeat itself with some precision, and the delay path was doubled up so that you could fill in the first 40nsec from the delayed version of the previous signal, while going on to sample from the closest trigger edge after than 40nsec.

http://www.sciencedirect.com/science/article/pii/016793179090015L

-- 
Bill Sloman, Sydney

[toc] | [prev] | [next] | [standalone]

#453012

<bill.sloman@ieee.org> wrote in message 
news:b4b79f6b-d3cc-48d8-b56f-8d65e47ff3ba@googlegroups.com...
>
> https://www.onsemi.com/pub/Collateral/MC100EP196-D.PDF
>
> It has been around - initially as the MC100E196 - for at least twenty 
> years.
> There were similar parts on offer before that, but I don't know of any 
> that stayed in production.
>

Oops, I mean to add I was talking about MCUs equipped with such 
functionality.

But yeah, there are special purpose things like that, too, but usually with 
quirks, like the tempco.

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com 

[toc] | [prev] | [next] | [standalone]

#452627

On 3/19/2017 1:42 PM, dagmargoodboat@yahoo.com wrote:
> On Saturday, March 18, 2017 at 7:40:03 PM UTC-4, rickman wrote:
>> On 3/18/2017 7:25 PM, John Larkin wrote:
>>> On Sat, 18 Mar 2017 17:02:36 -0500, "Tim Williams"
>>> <tiwill@seventransistorlabs.com> wrote:
>>>
>>>> I picked up some RUM001L02T2CL that are a hell of a lot smaller
>>>> (electrically) than garden-variety 2N7002 or BSS138.  For that matter, quite
>>>> a bit smaller (physically) too!
>>>>
>>>> The timing edge into 220pF looks blameless.  At 22pF there may be a bit of
>>>> hook, but not enough to matter (<10%?).
>>>>
>>>> The lower drain voltage rating means "logic level" is compatible even with
>>>> modern low voltage logic.
>>>>
>>>> Should be pretty okay at RF too, given the power limitation.
>>>>
>>>> Tim
>>>
>>> That's a nice part. Crss is only 1.7 pF, and one could reduce the gate
>>> drive to further reduce charge injection into the ramp cap.
>>>
>>> 2.5 volts into the gate, 1.7 to 100 pf (my cap) is just 40 millivolts
>>> of jump.
>>>
>>> It computes to 200 mV with a 22pF cap, but the channel is still
>>> conducting for part of the gate turn-off swing, so it will be even
>>> less. Needs a breadboard or a good Spice model to be sure.
>>
>> Here's a circuit you won't need to spice.
>>
>>         ___                 ___
>>     ___|      .-----.   ___|   |___
>>     ---->>----| MCU |---->>----
>>               '-----'
>>
>> You can set a delay, a pulse width, active edge or have it count edges
>> before emitting a pulse.  Different delays on the rising and falling
>> edge is possible.  A wide variety of things can be done and changed on
>> the fly.  The clock can be internal with a good accuracy.  The magic of
>> digital logic can do so much.
>>
>> --
>>
>> Rick C
>
> Very nice.  Now give it pS resolution and jitter and you'll be up to where
> John was roughly thirty years ago.

I don't see where anyone was asking for ps resolution or jitter.

-- 

Rick C

[toc] | [prev] | [next] | [standalone]

#452631

On 20/03/17 09:47, rickman wrote:
> On 3/19/2017 1:42 PM, dagmargoodboat@yahoo.com wrote:
>> On Saturday, March 18, 2017 at 7:40:03 PM UTC-4, rickman wrote:
>>> On 3/18/2017 7:25 PM, John Larkin wrote:
>>>> On Sat, 18 Mar 2017 17:02:36 -0500, "Tim Williams"
>>>> <tiwill@seventransistorlabs.com> wrote:
>>>>
>>>>> I picked up some RUM001L02T2CL that are a hell of a lot smaller
>>>>> (electrically) than garden-variety 2N7002 or BSS138.  For that
>>>>> matter, quite
>>>>> a bit smaller (physically) too!
>>>>>
>>>>> The timing edge into 220pF looks blameless.  At 22pF there may be a
>>>>> bit of
>>>>> hook, but not enough to matter (<10%?).
>>>>>
>>>>> The lower drain voltage rating means "logic level" is compatible
>>>>> even with
>>>>> modern low voltage logic.
>>>>>
>>>>> Should be pretty okay at RF too, given the power limitation.
>>>>>
>>>>> Tim
>>>>
>>>> That's a nice part. Crss is only 1.7 pF, and one could reduce the gate
>>>> drive to further reduce charge injection into the ramp cap.
>>>>
>>>> 2.5 volts into the gate, 1.7 to 100 pf (my cap) is just 40 millivolts
>>>> of jump.
>>>>
>>>> It computes to 200 mV with a 22pF cap, but the channel is still
>>>> conducting for part of the gate turn-off swing, so it will be even
>>>> less. Needs a breadboard or a good Spice model to be sure.
>>>
>>> Here's a circuit you won't need to spice.
>>>
>>>         ___                 ___
>>>     ___|      .-----.   ___|   |___
>>>     ---->>----| MCU |---->>----
>>>               '-----'
>>>
>>> You can set a delay, a pulse width, active edge or have it count edges
>>> before emitting a pulse.  Different delays on the rising and falling
>>> edge is possible.  A wide variety of things can be done and changed on
>>> the fly.  The clock can be internal with a good accuracy.  The magic of
>>> digital logic can do so much.
>>>
>>> --
>>>
>>> Rick C
>>
>> Very nice.  Now give it pS resolution and jitter and you'll be up to
>> where
>> John was roughly thirty years ago.

> I don't see where anyone was asking for ps resolution or jitter.

Then why do you think he was worrying about charge injection into 22pF?
You just weren't paying attention.

[toc] | [prev] | [next] | [standalone]

#452634

On Mon, 20 Mar 2017 09:55:16 +1100, Clifford Heath
<no.spam@please.net> wrote:

>On 20/03/17 09:47, rickman wrote:
>> On 3/19/2017 1:42 PM, dagmargoodboat@yahoo.com wrote:
>>> On Saturday, March 18, 2017 at 7:40:03 PM UTC-4, rickman wrote:
>>>> On 3/18/2017 7:25 PM, John Larkin wrote:
>>>>> On Sat, 18 Mar 2017 17:02:36 -0500, "Tim Williams"
>>>>> <tiwill@seventransistorlabs.com> wrote:
>>>>>
>>>>>> I picked up some RUM001L02T2CL that are a hell of a lot smaller
>>>>>> (electrically) than garden-variety 2N7002 or BSS138.  For that
>>>>>> matter, quite
>>>>>> a bit smaller (physically) too!
>>>>>>
>>>>>> The timing edge into 220pF looks blameless.  At 22pF there may be a
>>>>>> bit of
>>>>>> hook, but not enough to matter (<10%?).
>>>>>>
>>>>>> The lower drain voltage rating means "logic level" is compatible
>>>>>> even with
>>>>>> modern low voltage logic.
>>>>>>
>>>>>> Should be pretty okay at RF too, given the power limitation.
>>>>>>
>>>>>> Tim
>>>>>
>>>>> That's a nice part. Crss is only 1.7 pF, and one could reduce the gate
>>>>> drive to further reduce charge injection into the ramp cap.
>>>>>
>>>>> 2.5 volts into the gate, 1.7 to 100 pf (my cap) is just 40 millivolts
>>>>> of jump.
>>>>>
>>>>> It computes to 200 mV with a 22pF cap, but the channel is still
>>>>> conducting for part of the gate turn-off swing, so it will be even
>>>>> less. Needs a breadboard or a good Spice model to be sure.
>>>>
>>>> Here's a circuit you won't need to spice.
>>>>
>>>>         ___                 ___
>>>>     ___|      .-----.   ___|   |___
>>>>     ---->>----| MCU |---->>----
>>>>               '-----'
>>>>
>>>> You can set a delay, a pulse width, active edge or have it count edges
>>>> before emitting a pulse.  Different delays on the rising and falling
>>>> edge is possible.  A wide variety of things can be done and changed on
>>>> the fly.  The clock can be internal with a good accuracy.  The magic of
>>>> digital logic can do so much.
>>>>
>>>> --
>>>>
>>>> Rick C
>>>
>>> Very nice.  Now give it pS resolution and jitter and you'll be up to
>>> where
>>> John was roughly thirty years ago.
>
>> I don't see where anyone was asking for ps resolution or jitter.
>
>Then why do you think he was worrying about charge injection into 22pF?
>You just weren't paying attention.

Win was using a 22 pF ramp cap. My circuit switched between two caps,
100 pF and 10 nF. Charge injection is still a concern at 100 pF. The
ramp starts in the wrong direction (down instead of up) and takes a
while to get sensible.

I figured that the 100 pF cap would give me a 25 ns ramp, with maybe
100 ps settability (turning a pot) and maybe 10 or 20 ps RMS jitter.
Numbers like that; this is a cheap circuit.

Ricky is obnoxious, which I could tolerate if he was very good at
anything.


-- 

John Larkin         Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

[toc] | [prev] | [next] | [standalone]

#452581

"John Larkin" <jjlarkin@highlandtechnology.com> wrote in message 
news:o5grcchojd4qvdekiujn7qm31gos9bovol@4ax.com...
> It computes to 200 mV with a 22pF cap, but the channel is still
> conducting for part of the gate turn-off swing, so it will be even
> less. Needs a breadboard or a good Spice model to be sure.

Rohm provides a LEVEL=3 SPICE model.  No package parasitics.  Seems okay, 
but I haven't done detailed comparisons or anything.

They do seem to be ESD or temperature sensitive.  Between the small size and 
my loose ESD controls (namely, no antistatic mat and such), they're a bugger 
to hand solder reliably...

I think there are some dual MOSFETs of similar stature, too, which may be of 
interest to you.

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com 

[toc] | [prev] | [next] | [standalone]

Page 1 of 2  [1] 2  Next page →

Back to top | Article view | sci.electronics.design

csiph-web