Groups > sci.electronics.design > #452499

Re: bad, better delay circuits

From	rickman <gnuarm@gmail.com>
Newsgroups	sci.electronics.design
Subject	Re: bad, better delay circuits
Date	2017-03-18 19:40 -0400
Organization	A noiseless patient Spider
Message-ID	<oakgb3$u7m$1@dont-email.me> (permalink)
References	<1roqcclua35sdrn6jduc9q0folr3fg8oqu@4ax.com> <oakakg$ars$1@dont-email.me> <o5grcchojd4qvdekiujn7qm31gos9bovol@4ax.com>

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On 3/18/2017 7:25 PM, John Larkin wrote:
> On Sat, 18 Mar 2017 17:02:36 -0500, "Tim Williams"
> <tiwill@seventransistorlabs.com> wrote:
>
>> I picked up some RUM001L02T2CL that are a hell of a lot smaller
>> (electrically) than garden-variety 2N7002 or BSS138.  For that matter, quite
>> a bit smaller (physically) too!
>>
>> The timing edge into 220pF looks blameless.  At 22pF there may be a bit of
>> hook, but not enough to matter (<10%?).
>>
>> The lower drain voltage rating means "logic level" is compatible even with
>> modern low voltage logic.
>>
>> Should be pretty okay at RF too, given the power limitation.
>>
>> Tim
>
> That's a nice part. Crss is only 1.7 pF, and one could reduce the gate
> drive to further reduce charge injection into the ramp cap.
>
> 2.5 volts into the gate, 1.7 to 100 pf (my cap) is just 40 millivolts
> of jump.
>
> It computes to 200 mV with a 22pF cap, but the channel is still
> conducting for part of the gate turn-off swing, so it will be even
> less. Needs a breadboard or a good Spice model to be sure.

Here's a circuit you won't need to spice.

        ___                 ___
    ___|      .-----.   ___|   |___
    ---->>----| MCU |---->>----
              '-----'

You can set a delay, a pulse width, active edge or have it count edges 
before emitting a pulse.  Different delays on the rising and falling 
edge is possible.  A wide variety of things can be done and changed on 
the fly.  The clock can be internal with a good accuracy.  The magic of 
digital logic can do so much.

-- 

Rick C

Thread

bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-18 10:04 -0700
  Re: bad, better delay circuits Winfield Hill <hill@rowland.harvard.edu> - 2017-03-18 12:29 -0700
    Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-18 16:15 -0700
      Re: bad, better delay circuits Winfield Hill <hill@rowland.harvard.edu> - 2017-03-18 19:08 -0700
  Re: bad, better delay circuits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-18 17:02 -0500
    Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-18 16:25 -0700
      Re: bad, better delay circuits rickman <gnuarm@gmail.com> - 2017-03-18 19:40 -0400
        Re: bad, better delay circuits dagmargoodboat@yahoo.com - 2017-03-19 10:42 -0700
          Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-19 15:37 -0700
            Re: bad, better delay circuits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-19 22:24 -0500
              Re: bad, better delay circuits dagmargoodboat@yahoo.com - 2017-03-20 08:58 -0700
                Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-20 09:42 -0700
                Re: bad, better delay circuits Robert Baer <robertbaer@localnet.com> - 2017-03-20 23:55 -0800
                Re: bad, better delay circuits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-21 00:46 -0500
              Re: bad, better delay circuits bill.sloman@ieee.org - 2017-03-21 22:54 -0700
                Re: bad, better delay circuits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-22 02:10 -0500
          Re: bad, better delay circuits rickman <gnuarm@gmail.com> - 2017-03-19 18:47 -0400
            Re: bad, better delay circuits Clifford Heath <no.spam@please.net> - 2017-03-20 09:55 +1100
              Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-19 16:12 -0700
      Re: bad, better delay circuits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-19 10:32 -0500
  Re: bad, better delay circuits Clifford Heath <no.spam@please.net> - 2017-03-19 13:36 +1100
    Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-18 19:44 -0700
      Re: bad, better delay circuits Clifford Heath <no.spam@please.net> - 2017-03-19 15:58 +1100
        Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-19 15:43 -0700
          Re: bad, better delay circuits Winfield Hill <hill@rowland.harvard.edu> - 2017-03-19 17:54 -0700
            Re: bad, better delay circuits Clifford Heath <no.spam@please.net> - 2017-03-20 12:44 +1100
              Re: bad, better delay circuits Winfield Hill <hill@rowland.harvard.edu> - 2017-03-20 12:22 -0700
                Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-20 15:49 -0700
  Re: bad, better delay circuits whit3rd <whit3rd@gmail.com> - 2017-03-18 23:51 -0700
    Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-19 08:22 -0700
  Re: bad, better delay circuits George Herold <gherold@teachspin.com> - 2017-03-20 17:55 -0700
  Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-22 08:54 -0700
    Re: bad, better delay circuits JM <dontreplytothis173@gmail.com> - 2017-03-22 16:02 +0000
      Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-22 09:47 -0700
    Re: bad, better delay circuits Winfield Hill <hill@rowland.harvard.edu> - 2017-03-22 10:31 -0700
      Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-22 10:52 -0700

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