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Parasitics?

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  Parasitics? rickman <gnuarm@gmail.com> - 2017-03-16 19:44 -0400
    Re: Parasitics? bloggs.fredbloggs.fred@gmail.com - 2017-03-16 16:48 -0700
    Re: Parasitics? Sylvia Else <sylvia@not.at.this.address> - 2017-03-17 10:59 +1100
      Re: Parasitics? rickman <gnuarm@gmail.com> - 2017-03-16 20:19 -0400
    Re: Parasitics? Sylvia Else <sylvia@not.at.this.address> - 2017-03-17 12:21 +1100
      Re: Parasitics? rickman <gnuarm@gmail.com> - 2017-03-16 23:16 -0400
        Re: Parasitics? Sylvia Else <sylvia@not.at.this.address> - 2017-03-17 14:51 +1100
          Re: Parasitics? rickman <gnuarm@gmail.com> - 2017-03-17 00:57 -0400
            Re: Parasitics? bloggs.fredbloggs.fred@gmail.com - 2017-03-18 01:36 -0700
              Re: Parasitics? rickman <gnuarm@gmail.com> - 2017-03-18 05:45 -0400
                Re: Parasitics? bloggs.fredbloggs.fred@gmail.com - 2017-03-18 06:33 -0700
                  Re: Parasitics? rickman <gnuarm@gmail.com> - 2017-03-18 12:22 -0400
                    Re: Parasitics? Sylvia Else <sylvia@not.at.this.address> - 2017-03-24 13:30 +1100
                      Re: Parasitics? rickman <gnuarm@gmail.com> - 2017-03-24 00:36 -0400
                        Re: Parasitics? Sylvia Else <sylvia@not.at.this.address> - 2017-03-24 16:10 +1100
    Re: Parasitics? "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-17 01:42 -0500
      Re: Parasitics? rickman <gnuarm@gmail.com> - 2017-03-17 04:11 -0400
    Re: Parasitics? Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> - 2017-03-17 09:53 -0400
      Re: Parasitics? Cursitor Doom <curd@notformail.com> - 2017-03-17 18:52 +0000

#452193 — Parasitics?

I'm running a simulation where I'm pumping charge into a capacitor to 
generate a voltage.  A transistor emitter/source is connected to the 
positive rail and the collector/drain is connected to a 1 nF cap through 
a 47k resistor.  When the base/gate is driven high to shut off the 
current I see the current go up initially then taking almost 2 us to 
shut off.  I've tried 2N3906 and BSS84 and a couple others selected 
randomly.  The switching period is around 8 uS.

Is this from the parasitic capacitance in the transistor?  The BSS84 
only has 1 nC gate charge and still the effect is very pronounced.

Is there a way to mitigate this effect other than using a larger cap and 
smaller resistors?

-- 

Rick C

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#452195

On Thursday, March 16, 2017 at 7:44:40 PM UTC-4, rickman wrote:
> I'm running a simulation where I'm pumping charge into a capacitor to 
> generate a voltage.  A transistor emitter/source is connected to the 
> positive rail and the collector/drain is connected to a 1 nF cap through 
> a 47k resistor.  When the base/gate is driven high to shut off the 
> current I see the current go up initially then taking almost 2 us to 
> shut off.  I've tried 2N3906 and BSS84 and a couple others selected 
> randomly.  The switching period is around 8 uS.
> 
> Is this from the parasitic capacitance in the transistor?  The BSS84 
> only has 1 nC gate charge and still the effect is very pronounced.
> 
> Is there a way to mitigate this effect other than using a larger cap and 
> smaller resistors?
> 
> -- 
> 
> Rick C

The current increase at shut-off is charge injection into base- collector junction.

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#452198

On 17/03/2017 10:44 AM, rickman wrote:
> I'm running a simulation where I'm pumping charge into a capacitor to
> generate a voltage.  A transistor emitter/source is connected to the
> positive rail and the collector/drain is connected to a 1 nF cap through
> a 47k resistor.  When the base/gate is driven high to shut off the
> current I see the current go up initially then taking almost 2 us to
> shut off.  I've tried 2N3906 and BSS84 and a couple others selected
> randomly.  The switching period is around 8 uS.
>
> Is this from the parasitic capacitance in the transistor?  The BSS84
> only has 1 nC gate charge and still the effect is very pronounced.
>
> Is there a way to mitigate this effect other than using a larger cap and
> smaller resistors?
>

If your problem only related to the pnp transistor, I'd say it was 
caused by charge storage. That you're having the same problem with a FET 
suggests another problem.

Perhaps you could provide the exact circuit you're using.

Sylvia.

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#452201

On 3/16/2017 7:59 PM, Sylvia Else wrote:
> On 17/03/2017 10:44 AM, rickman wrote:
>> I'm running a simulation where I'm pumping charge into a capacitor to
>> generate a voltage.  A transistor emitter/source is connected to the
>> positive rail and the collector/drain is connected to a 1 nF cap through
>> a 47k resistor.  When the base/gate is driven high to shut off the
>> current I see the current go up initially then taking almost 2 us to
>> shut off.  I've tried 2N3906 and BSS84 and a couple others selected
>> randomly.  The switching period is around 8 uS.
>>
>> Is this from the parasitic capacitance in the transistor?  The BSS84
>> only has 1 nC gate charge and still the effect is very pronounced.
>>
>> Is there a way to mitigate this effect other than using a larger cap and
>> smaller resistors?
>>
>
> If your problem only related to the pnp transistor, I'd say it was
> caused by charge storage. That you're having the same problem with a FET
> suggests another problem.
>
> Perhaps you could provide the exact circuit you're using.


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-- 

Rick C

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#452212

On 17/03/2017 10:44 AM, rickman wrote:
> I'm running a simulation where I'm pumping charge into a capacitor to
> generate a voltage.  A transistor emitter/source is connected to the
> positive rail and the collector/drain is connected to a 1 nF cap through
> a 47k resistor.  When the base/gate is driven high to shut off the
> current I see the current go up initially then taking almost 2 us to
> shut off.  I've tried 2N3906 and BSS84 and a couple others selected
> randomly.  The switching period is around 8 uS.
>
> Is this from the parasitic capacitance in the transistor?  The BSS84
> only has 1 nC gate charge and still the effect is very pronounced.
>
> Is there a way to mitigate this effect other than using a larger cap and
> smaller resistors?
>
When you try to drive the gate high, the gate-drain capacitance has to 
be charged, and the only way than can happen is for current to flow 
through R3. A back of the envelope calculation suggests that will take 
about the time you're seeing.

To get it to switch more quickly, you need to reduce R3, or provide some 
other path for the current.

A diode in series with R3, and a 1K resistor from the drain to ground 
improves things substantially.

Sylvia.

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#452225

On 3/16/2017 9:21 PM, Sylvia Else wrote:
> On 17/03/2017 10:44 AM, rickman wrote:
>> I'm running a simulation where I'm pumping charge into a capacitor to
>> generate a voltage.  A transistor emitter/source is connected to the
>> positive rail and the collector/drain is connected to a 1 nF cap through
>> a 47k resistor.  When the base/gate is driven high to shut off the
>> current I see the current go up initially then taking almost 2 us to
>> shut off.  I've tried 2N3906 and BSS84 and a couple others selected
>> randomly.  The switching period is around 8 uS.
>>
>> Is this from the parasitic capacitance in the transistor?  The BSS84
>> only has 1 nC gate charge and still the effect is very pronounced.
>>
>> Is there a way to mitigate this effect other than using a larger cap and
>> smaller resistors?
>>
> When you try to drive the gate high, the gate-drain capacitance has to
> be charged, and the only way than can happen is for current to flow
> through R3. A back of the envelope calculation suggests that will take
> about the time you're seeing.
>
> To get it to switch more quickly, you need to reduce R3, or provide some
> other path for the current.
>
> A diode in series with R3, and a 1K resistor from the drain to ground
> improves things substantially.

That actually makes things worse by substituting the capacitance of the 
diode through the 1k resistor for the capacitance of the transistor.

I was trying to use a very low power approach by injecting charge onto a 
capacitor which would have a very low drain from it.  But if low value 
resistors have to be added, I can just use a dithered pullup/pulldown 
instead.  That may also have current injection, but it should be 
approximately equal in both directions because of the push-pull output.

-- 

Rick C

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#452229

On 17/03/2017 2:16 PM, rickman wrote:
> On 3/16/2017 9:21 PM, Sylvia Else wrote:
>> On 17/03/2017 10:44 AM, rickman wrote:
>>> I'm running a simulation where I'm pumping charge into a capacitor to
>>> generate a voltage.  A transistor emitter/source is connected to the
>>> positive rail and the collector/drain is connected to a 1 nF cap through
>>> a 47k resistor.  When the base/gate is driven high to shut off the
>>> current I see the current go up initially then taking almost 2 us to
>>> shut off.  I've tried 2N3906 and BSS84 and a couple others selected
>>> randomly.  The switching period is around 8 uS.
>>>
>>> Is this from the parasitic capacitance in the transistor?  The BSS84
>>> only has 1 nC gate charge and still the effect is very pronounced.
>>>
>>> Is there a way to mitigate this effect other than using a larger cap and
>>> smaller resistors?
>>>
>> When you try to drive the gate high, the gate-drain capacitance has to
>> be charged, and the only way than can happen is for current to flow
>> through R3. A back of the envelope calculation suggests that will take
>> about the time you're seeing.
>>
>> To get it to switch more quickly, you need to reduce R3, or provide some
>> other path for the current.
>>
>> A diode in series with R3, and a 1K resistor from the drain to ground
>> improves things substantially.
>
> That actually makes things worse by substituting the capacitance of the
> diode through the 1k resistor for the capacitance of the transistor.
>
> I was trying to use a very low power approach by injecting charge onto a
> capacitor which would have a very low drain from it.  But if low value
> resistors have to be added, I can just use a dithered pullup/pulldown
> instead.  That may also have current injection, but it should be
> approximately equal in both directions because of the push-pull output.
>

I had in mind this. The current through R3 reverses, then returns to 
zero in 190ns.

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#452231

On 3/16/2017 11:51 PM, Sylvia Else wrote:
> On 17/03/2017 2:16 PM, rickman wrote:
>> On 3/16/2017 9:21 PM, Sylvia Else wrote:
>>> On 17/03/2017 10:44 AM, rickman wrote:
>>>> I'm running a simulation where I'm pumping charge into a capacitor to
>>>> generate a voltage.  A transistor emitter/source is connected to the
>>>> positive rail and the collector/drain is connected to a 1 nF cap
>>>> through
>>>> a 47k resistor.  When the base/gate is driven high to shut off the
>>>> current I see the current go up initially then taking almost 2 us to
>>>> shut off.  I've tried 2N3906 and BSS84 and a couple others selected
>>>> randomly.  The switching period is around 8 uS.
>>>>
>>>> Is this from the parasitic capacitance in the transistor?  The BSS84
>>>> only has 1 nC gate charge and still the effect is very pronounced.
>>>>
>>>> Is there a way to mitigate this effect other than using a larger cap
>>>> and
>>>> smaller resistors?
>>>>
>>> When you try to drive the gate high, the gate-drain capacitance has to
>>> be charged, and the only way than can happen is for current to flow
>>> through R3. A back of the envelope calculation suggests that will take
>>> about the time you're seeing.
>>>
>>> To get it to switch more quickly, you need to reduce R3, or provide some
>>> other path for the current.
>>>
>>> A diode in series with R3, and a 1K resistor from the drain to ground
>>> improves things substantially.
>>
>> That actually makes things worse by substituting the capacitance of the
>> diode through the 1k resistor for the capacitance of the transistor.
>>
>> I was trying to use a very low power approach by injecting charge onto a
>> capacitor which would have a very low drain from it.  But if low value
>> resistors have to be added, I can just use a dithered pullup/pulldown
>> instead.  That may also have current injection, but it should be
>> approximately equal in both directions because of the push-pull output.
>>
>
> I had in mind this. The current through R3 reverses, then returns to
> zero in 190ns.

Yes, that's what I modeled.  I see large current spikes on both edges of 
the pulse.  Regardless, I won't be using a discrete transistor.  I'll be 
using the output from an FPGA.  Depending on the pulse width of the 
output, the current in R2 is around 1 mA which is as much as the entire 
rest of the project.

I can use a large resistor in series with the output into the cap and 
drive it high and low for a range of duty cycles.  That will get me what 
I need.  This circuit only needs to source voltage, so I thought it 
would use less current to only pull high.  We'll see what the real 
circuit does when I use the actual FPGA output.  It doesn't have to be 
perfectly linear with duty cycle, but it does need to at least be 
monotonic.

-- 

Rick C

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#452385

On Friday, March 17, 2017 at 12:57:57 AM UTC-4, rickman wrote:
> On 3/16/2017 11:51 PM, Sylvia Else wrote:
> > On 17/03/2017 2:16 PM, rickman wrote:
> >> On 3/16/2017 9:21 PM, Sylvia Else wrote:
> >>> On 17/03/2017 10:44 AM, rickman wrote:
> >>>> I'm running a simulation where I'm pumping charge into a capacitor to
> >>>> generate a voltage.  A transistor emitter/source is connected to the
> >>>> positive rail and the collector/drain is connected to a 1 nF cap
> >>>> through
> >>>> a 47k resistor.  When the base/gate is driven high to shut off the
> >>>> current I see the current go up initially then taking almost 2 us to
> >>>> shut off.  I've tried 2N3906 and BSS84 and a couple others selected
> >>>> randomly.  The switching period is around 8 uS.
> >>>>
> >>>> Is this from the parasitic capacitance in the transistor?  The BSS84
> >>>> only has 1 nC gate charge and still the effect is very pronounced.
> >>>>
> >>>> Is there a way to mitigate this effect other than using a larger cap
> >>>> and
> >>>> smaller resistors?
> >>>>
> >>> When you try to drive the gate high, the gate-drain capacitance has to
> >>> be charged, and the only way than can happen is for current to flow
> >>> through R3. A back of the envelope calculation suggests that will take
> >>> about the time you're seeing.
> >>>
> >>> To get it to switch more quickly, you need to reduce R3, or provide some
> >>> other path for the current.
> >>>
> >>> A diode in series with R3, and a 1K resistor from the drain to ground
> >>> improves things substantially.
> >>
> >> That actually makes things worse by substituting the capacitance of the
> >> diode through the 1k resistor for the capacitance of the transistor.
> >>
> >> I was trying to use a very low power approach by injecting charge onto a
> >> capacitor which would have a very low drain from it.  But if low value
> >> resistors have to be added, I can just use a dithered pullup/pulldown
> >> instead.  That may also have current injection, but it should be
> >> approximately equal in both directions because of the push-pull output.
> >>
> >
> > I had in mind this. The current through R3 reverses, then returns to
> > zero in 190ns.
> 
> Yes, that's what I modeled.  I see large current spikes on both edges of 
> the pulse.  Regardless, I won't be using a discrete transistor.  I'll be 
> using the output from an FPGA.  Depending on the pulse width of the 
> output, the current in R2 is around 1 mA which is as much as the entire 
> rest of the project.
> 
> I can use a large resistor in series with the output into the cap and 
> drive it high and low for a range of duty cycles.  That will get me what 
> I need.  This circuit only needs to source voltage, so I thought it 
> would use less current to only pull high.  We'll see what the real 
> circuit does when I use the actual FPGA output.  It doesn't have to be 
> perfectly linear with duty cycle, but it does need to at least be 
> monotonic.

Uh-huh, and what is the problem you can't simply drive this flea power RC from the FPGA directly? You do know how an RC works? Right?

> 
> -- 
> 
> Rick C

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#452394

On 3/18/2017 4:36 AM, bloggs.fredbloggs.fred@gmail.com wrote:
> On Friday, March 17, 2017 at 12:57:57 AM UTC-4, rickman wrote:
>> On 3/16/2017 11:51 PM, Sylvia Else wrote:
>>> On 17/03/2017 2:16 PM, rickman wrote:
>>>> On 3/16/2017 9:21 PM, Sylvia Else wrote:
>>>>> On 17/03/2017 10:44 AM, rickman wrote:
>>>>>> I'm running a simulation where I'm pumping charge into a capacitor to
>>>>>> generate a voltage.  A transistor emitter/source is connected to the
>>>>>> positive rail and the collector/drain is connected to a 1 nF cap
>>>>>> through
>>>>>> a 47k resistor.  When the base/gate is driven high to shut off the
>>>>>> current I see the current go up initially then taking almost 2 us to
>>>>>> shut off.  I've tried 2N3906 and BSS84 and a couple others selected
>>>>>> randomly.  The switching period is around 8 uS.
>>>>>>
>>>>>> Is this from the parasitic capacitance in the transistor?  The BSS84
>>>>>> only has 1 nC gate charge and still the effect is very pronounced.
>>>>>>
>>>>>> Is there a way to mitigate this effect other than using a larger cap
>>>>>> and
>>>>>> smaller resistors?
>>>>>>
>>>>> When you try to drive the gate high, the gate-drain capacitance has to
>>>>> be charged, and the only way than can happen is for current to flow
>>>>> through R3. A back of the envelope calculation suggests that will take
>>>>> about the time you're seeing.
>>>>>
>>>>> To get it to switch more quickly, you need to reduce R3, or provide some
>>>>> other path for the current.
>>>>>
>>>>> A diode in series with R3, and a 1K resistor from the drain to ground
>>>>> improves things substantially.
>>>>
>>>> That actually makes things worse by substituting the capacitance of the
>>>> diode through the 1k resistor for the capacitance of the transistor.
>>>>
>>>> I was trying to use a very low power approach by injecting charge onto a
>>>> capacitor which would have a very low drain from it.  But if low value
>>>> resistors have to be added, I can just use a dithered pullup/pulldown
>>>> instead.  That may also have current injection, but it should be
>>>> approximately equal in both directions because of the push-pull output.
>>>>
>>>
>>> I had in mind this. The current through R3 reverses, then returns to
>>> zero in 190ns.
>>
>> Yes, that's what I modeled.  I see large current spikes on both edges of
>> the pulse.  Regardless, I won't be using a discrete transistor.  I'll be
>> using the output from an FPGA.  Depending on the pulse width of the
>> output, the current in R2 is around 1 mA which is as much as the entire
>> rest of the project.
>>
>> I can use a large resistor in series with the output into the cap and
>> drive it high and low for a range of duty cycles.  That will get me what
>> I need.  This circuit only needs to source voltage, so I thought it
>> would use less current to only pull high.  We'll see what the real
>> circuit does when I use the actual FPGA output.  It doesn't have to be
>> perfectly linear with duty cycle, but it does need to at least be
>> monotonic.
>
> Uh-huh, and what is the problem you can't simply drive this flea power RC from the FPGA directly? You do know how an RC works? Right?

I'm not sure what you are talking about.  I will be driving the RC 
directly from the FPGA output.

I don't have FPGA outputs in the simulation, so I was using a FET as a 
model.  Since it appears there are issues with charge injection when 
driving a high impedance, I will just have to work that out on the bench.

-- 

Rick C

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#452414

On Saturday, March 18, 2017 at 5:45:07 AM UTC-4, rickman wrote:
> On 3/18/2017 4:36 AM, bloggs.fredbloggs.fred@gmail.com wrote:
> > On Friday, March 17, 2017 at 12:57:57 AM UTC-4, rickman wrote:
> >> On 3/16/2017 11:51 PM, Sylvia Else wrote:
> >>> On 17/03/2017 2:16 PM, rickman wrote:
> >>>> On 3/16/2017 9:21 PM, Sylvia Else wrote:
> >>>>> On 17/03/2017 10:44 AM, rickman wrote:
> >>>>>> I'm running a simulation where I'm pumping charge into a capacitor to
> >>>>>> generate a voltage.  A transistor emitter/source is connected to the
> >>>>>> positive rail and the collector/drain is connected to a 1 nF cap
> >>>>>> through
> >>>>>> a 47k resistor.  When the base/gate is driven high to shut off the
> >>>>>> current I see the current go up initially then taking almost 2 us to
> >>>>>> shut off.  I've tried 2N3906 and BSS84 and a couple others selected
> >>>>>> randomly.  The switching period is around 8 uS.
> >>>>>>
> >>>>>> Is this from the parasitic capacitance in the transistor?  The BSS84
> >>>>>> only has 1 nC gate charge and still the effect is very pronounced.
> >>>>>>
> >>>>>> Is there a way to mitigate this effect other than using a larger cap
> >>>>>> and
> >>>>>> smaller resistors?
> >>>>>>
> >>>>> When you try to drive the gate high, the gate-drain capacitance has to
> >>>>> be charged, and the only way than can happen is for current to flow
> >>>>> through R3. A back of the envelope calculation suggests that will take
> >>>>> about the time you're seeing.
> >>>>>
> >>>>> To get it to switch more quickly, you need to reduce R3, or provide some
> >>>>> other path for the current.
> >>>>>
> >>>>> A diode in series with R3, and a 1K resistor from the drain to ground
> >>>>> improves things substantially.
> >>>>
> >>>> That actually makes things worse by substituting the capacitance of the
> >>>> diode through the 1k resistor for the capacitance of the transistor.
> >>>>
> >>>> I was trying to use a very low power approach by injecting charge onto a
> >>>> capacitor which would have a very low drain from it.  But if low value
> >>>> resistors have to be added, I can just use a dithered pullup/pulldown
> >>>> instead.  That may also have current injection, but it should be
> >>>> approximately equal in both directions because of the push-pull output.
> >>>>
> >>>
> >>> I had in mind this. The current through R3 reverses, then returns to
> >>> zero in 190ns.
> >>
> >> Yes, that's what I modeled.  I see large current spikes on both edges of
> >> the pulse.  Regardless, I won't be using a discrete transistor.  I'll be
> >> using the output from an FPGA.  Depending on the pulse width of the
> >> output, the current in R2 is around 1 mA which is as much as the entire
> >> rest of the project.
> >>
> >> I can use a large resistor in series with the output into the cap and
> >> drive it high and low for a range of duty cycles.  That will get me what
> >> I need.  This circuit only needs to source voltage, so I thought it
> >> would use less current to only pull high.  We'll see what the real
> >> circuit does when I use the actual FPGA output.  It doesn't have to be
> >> perfectly linear with duty cycle, but it does need to at least be
> >> monotonic.
> >
> > Uh-huh, and what is the problem you can't simply drive this flea power RC from the FPGA directly? You do know how an RC works? Right?
> 
> I'm not sure what you are talking about.  I will be driving the RC 
> directly from the FPGA output.
> 
> I don't have FPGA outputs in the simulation, so I was using a FET as a 
> model.  Since it appears there are issues with charge injection when 
> driving a high impedance, I will just have to work that out on the bench.

Huh? You think that circuit is representative of an FPGA CMOS output? Don't think so...

> 
> -- 
> 
> Rick C

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#452441

On 3/18/2017 9:33 AM, bloggs.fredbloggs.fred@gmail.com wrote:
> On Saturday, March 18, 2017 at 5:45:07 AM UTC-4, rickman wrote:
>> On 3/18/2017 4:36 AM, bloggs.fredbloggs.fred@gmail.com wrote:
>>> On Friday, March 17, 2017 at 12:57:57 AM UTC-4, rickman wrote:
>>>> On 3/16/2017 11:51 PM, Sylvia Else wrote:
>>>>> On 17/03/2017 2:16 PM, rickman wrote:
>>>>>> On 3/16/2017 9:21 PM, Sylvia Else wrote:
>>>>>>> On 17/03/2017 10:44 AM, rickman wrote:
>>>>>>>> I'm running a simulation where I'm pumping charge into a capacitor to
>>>>>>>> generate a voltage.  A transistor emitter/source is connected to the
>>>>>>>> positive rail and the collector/drain is connected to a 1 nF cap
>>>>>>>> through
>>>>>>>> a 47k resistor.  When the base/gate is driven high to shut off the
>>>>>>>> current I see the current go up initially then taking almost 2 us to
>>>>>>>> shut off.  I've tried 2N3906 and BSS84 and a couple others selected
>>>>>>>> randomly.  The switching period is around 8 uS.
>>>>>>>>
>>>>>>>> Is this from the parasitic capacitance in the transistor?  The BSS84
>>>>>>>> only has 1 nC gate charge and still the effect is very pronounced.
>>>>>>>>
>>>>>>>> Is there a way to mitigate this effect other than using a larger cap
>>>>>>>> and
>>>>>>>> smaller resistors?
>>>>>>>>
>>>>>>> When you try to drive the gate high, the gate-drain capacitance has to
>>>>>>> be charged, and the only way than can happen is for current to flow
>>>>>>> through R3. A back of the envelope calculation suggests that will take
>>>>>>> about the time you're seeing.
>>>>>>>
>>>>>>> To get it to switch more quickly, you need to reduce R3, or provide some
>>>>>>> other path for the current.
>>>>>>>
>>>>>>> A diode in series with R3, and a 1K resistor from the drain to ground
>>>>>>> improves things substantially.
>>>>>>
>>>>>> That actually makes things worse by substituting the capacitance of the
>>>>>> diode through the 1k resistor for the capacitance of the transistor.
>>>>>>
>>>>>> I was trying to use a very low power approach by injecting charge onto a
>>>>>> capacitor which would have a very low drain from it.  But if low value
>>>>>> resistors have to be added, I can just use a dithered pullup/pulldown
>>>>>> instead.  That may also have current injection, but it should be
>>>>>> approximately equal in both directions because of the push-pull output.
>>>>>>
>>>>>
>>>>> I had in mind this. The current through R3 reverses, then returns to
>>>>> zero in 190ns.
>>>>
>>>> Yes, that's what I modeled.  I see large current spikes on both edges of
>>>> the pulse.  Regardless, I won't be using a discrete transistor.  I'll be
>>>> using the output from an FPGA.  Depending on the pulse width of the
>>>> output, the current in R2 is around 1 mA which is as much as the entire
>>>> rest of the project.
>>>>
>>>> I can use a large resistor in series with the output into the cap and
>>>> drive it high and low for a range of duty cycles.  That will get me what
>>>> I need.  This circuit only needs to source voltage, so I thought it
>>>> would use less current to only pull high.  We'll see what the real
>>>> circuit does when I use the actual FPGA output.  It doesn't have to be
>>>> perfectly linear with duty cycle, but it does need to at least be
>>>> monotonic.
>>>
>>> Uh-huh, and what is the problem you can't simply drive this flea power RC from the FPGA directly? You do know how an RC works? Right?
>>
>> I'm not sure what you are talking about.  I will be driving the RC
>> directly from the FPGA output.
>>
>> I don't have FPGA outputs in the simulation, so I was using a FET as a
>> model.  Since it appears there are issues with charge injection when
>> driving a high impedance, I will just have to work that out on the bench.
>
> Huh? You think that circuit is representative of an FPGA CMOS output? Don't think so...

First order approximation, a FET.  I'm not going to try to model it more 
closely.  There's not much I can do with it other than vary the drive 
strenth/slew rate.  So as I said, I'll test it on the bench and see what 
I can get out of it.

-- 

Rick C

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#453322

On 19/03/2017 3:22 AM, rickman wrote:
> On 3/18/2017 9:33 AM, bloggs.fredbloggs.fred@gmail.com wrote:
>> On Saturday, March 18, 2017 at 5:45:07 AM UTC-4, rickman wrote:
>>> On 3/18/2017 4:36 AM, bloggs.fredbloggs.fred@gmail.com wrote:
>>>> On Friday, March 17, 2017 at 12:57:57 AM UTC-4, rickman wrote:
>>>>> On 3/16/2017 11:51 PM, Sylvia Else wrote:
>>>>>> On 17/03/2017 2:16 PM, rickman wrote:
>>>>>>> On 3/16/2017 9:21 PM, Sylvia Else wrote:
>>>>>>>> On 17/03/2017 10:44 AM, rickman wrote:
>>>>>>>>> I'm running a simulation where I'm pumping charge into a
>>>>>>>>> capacitor to
>>>>>>>>> generate a voltage.  A transistor emitter/source is connected
>>>>>>>>> to the
>>>>>>>>> positive rail and the collector/drain is connected to a 1 nF cap
>>>>>>>>> through
>>>>>>>>> a 47k resistor.  When the base/gate is driven high to shut off the
>>>>>>>>> current I see the current go up initially then taking almost 2
>>>>>>>>> us to
>>>>>>>>> shut off.  I've tried 2N3906 and BSS84 and a couple others
>>>>>>>>> selected
>>>>>>>>> randomly.  The switching period is around 8 uS.
>>>>>>>>>
>>>>>>>>> Is this from the parasitic capacitance in the transistor?  The
>>>>>>>>> BSS84
>>>>>>>>> only has 1 nC gate charge and still the effect is very pronounced.
>>>>>>>>>
>>>>>>>>> Is there a way to mitigate this effect other than using a
>>>>>>>>> larger cap
>>>>>>>>> and
>>>>>>>>> smaller resistors?
>>>>>>>>>
>>>>>>>> When you try to drive the gate high, the gate-drain capacitance
>>>>>>>> has to
>>>>>>>> be charged, and the only way than can happen is for current to flow
>>>>>>>> through R3. A back of the envelope calculation suggests that
>>>>>>>> will take
>>>>>>>> about the time you're seeing.
>>>>>>>>
>>>>>>>> To get it to switch more quickly, you need to reduce R3, or
>>>>>>>> provide some
>>>>>>>> other path for the current.
>>>>>>>>
>>>>>>>> A diode in series with R3, and a 1K resistor from the drain to
>>>>>>>> ground
>>>>>>>> improves things substantially.
>>>>>>>
>>>>>>> That actually makes things worse by substituting the capacitance
>>>>>>> of the
>>>>>>> diode through the 1k resistor for the capacitance of the transistor.
>>>>>>>
>>>>>>> I was trying to use a very low power approach by injecting charge
>>>>>>> onto a
>>>>>>> capacitor which would have a very low drain from it.  But if low
>>>>>>> value
>>>>>>> resistors have to be added, I can just use a dithered
>>>>>>> pullup/pulldown
>>>>>>> instead.  That may also have current injection, but it should be
>>>>>>> approximately equal in both directions because of the push-pull
>>>>>>> output.
>>>>>>>
>>>>>>
>>>>>> I had in mind this. The current through R3 reverses, then returns to
>>>>>> zero in 190ns.
>>>>>
>>>>> Yes, that's what I modeled.  I see large current spikes on both
>>>>> edges of
>>>>> the pulse.  Regardless, I won't be using a discrete transistor.
>>>>> I'll be
>>>>> using the output from an FPGA.  Depending on the pulse width of the
>>>>> output, the current in R2 is around 1 mA which is as much as the
>>>>> entire
>>>>> rest of the project.
>>>>>
>>>>> I can use a large resistor in series with the output into the cap and
>>>>> drive it high and low for a range of duty cycles.  That will get me
>>>>> what
>>>>> I need.  This circuit only needs to source voltage, so I thought it
>>>>> would use less current to only pull high.  We'll see what the real
>>>>> circuit does when I use the actual FPGA output.  It doesn't have to be
>>>>> perfectly linear with duty cycle, but it does need to at least be
>>>>> monotonic.
>>>>
>>>> Uh-huh, and what is the problem you can't simply drive this flea
>>>> power RC from the FPGA directly? You do know how an RC works? Right?
>>>
>>> I'm not sure what you are talking about.  I will be driving the RC
>>> directly from the FPGA output.
>>>
>>> I don't have FPGA outputs in the simulation, so I was using a FET as a
>>> model.  Since it appears there are issues with charge injection when
>>> driving a high impedance, I will just have to work that out on the
>>> bench.
>>
>> Huh? You think that circuit is representative of an FPGA CMOS output?
>> Don't think so...
>
> First order approximation, a FET.  I'm not going to try to model it more
> closely.  There's not much I can do with it other than vary the drive
> strenth/slew rate.  So as I said, I'll test it on the bench and see what
> I can get out of it.
>

The FPGA CMOS output is likely to be push-pull, which will make a big 
difference.

Sylvia.

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#453333

On 3/23/2017 10:30 PM, Sylvia Else wrote:
> On 19/03/2017 3:22 AM, rickman wrote:
>> On 3/18/2017 9:33 AM, bloggs.fredbloggs.fred@gmail.com wrote:
>>> On Saturday, March 18, 2017 at 5:45:07 AM UTC-4, rickman wrote:
>>>> On 3/18/2017 4:36 AM, bloggs.fredbloggs.fred@gmail.com wrote:
>>>>> On Friday, March 17, 2017 at 12:57:57 AM UTC-4, rickman wrote:
>>>>>> On 3/16/2017 11:51 PM, Sylvia Else wrote:
>>>>>>> On 17/03/2017 2:16 PM, rickman wrote:
>>>>>>>> On 3/16/2017 9:21 PM, Sylvia Else wrote:
>>>>>>>>> On 17/03/2017 10:44 AM, rickman wrote:
>>>>>>>>>> I'm running a simulation where I'm pumping charge into a
>>>>>>>>>> capacitor to
>>>>>>>>>> generate a voltage.  A transistor emitter/source is connected
>>>>>>>>>> to the
>>>>>>>>>> positive rail and the collector/drain is connected to a 1 nF cap
>>>>>>>>>> through
>>>>>>>>>> a 47k resistor.  When the base/gate is driven high to shut off
>>>>>>>>>> the
>>>>>>>>>> current I see the current go up initially then taking almost 2
>>>>>>>>>> us to
>>>>>>>>>> shut off.  I've tried 2N3906 and BSS84 and a couple others
>>>>>>>>>> selected
>>>>>>>>>> randomly.  The switching period is around 8 uS.
>>>>>>>>>>
>>>>>>>>>> Is this from the parasitic capacitance in the transistor?  The
>>>>>>>>>> BSS84
>>>>>>>>>> only has 1 nC gate charge and still the effect is very
>>>>>>>>>> pronounced.
>>>>>>>>>>
>>>>>>>>>> Is there a way to mitigate this effect other than using a
>>>>>>>>>> larger cap
>>>>>>>>>> and
>>>>>>>>>> smaller resistors?
>>>>>>>>>>
>>>>>>>>> When you try to drive the gate high, the gate-drain capacitance
>>>>>>>>> has to
>>>>>>>>> be charged, and the only way than can happen is for current to
>>>>>>>>> flow
>>>>>>>>> through R3. A back of the envelope calculation suggests that
>>>>>>>>> will take
>>>>>>>>> about the time you're seeing.
>>>>>>>>>
>>>>>>>>> To get it to switch more quickly, you need to reduce R3, or
>>>>>>>>> provide some
>>>>>>>>> other path for the current.
>>>>>>>>>
>>>>>>>>> A diode in series with R3, and a 1K resistor from the drain to
>>>>>>>>> ground
>>>>>>>>> improves things substantially.
>>>>>>>>
>>>>>>>> That actually makes things worse by substituting the capacitance
>>>>>>>> of the
>>>>>>>> diode through the 1k resistor for the capacitance of the
>>>>>>>> transistor.
>>>>>>>>
>>>>>>>> I was trying to use a very low power approach by injecting charge
>>>>>>>> onto a
>>>>>>>> capacitor which would have a very low drain from it.  But if low
>>>>>>>> value
>>>>>>>> resistors have to be added, I can just use a dithered
>>>>>>>> pullup/pulldown
>>>>>>>> instead.  That may also have current injection, but it should be
>>>>>>>> approximately equal in both directions because of the push-pull
>>>>>>>> output.
>>>>>>>>
>>>>>>>
>>>>>>> I had in mind this. The current through R3 reverses, then returns to
>>>>>>> zero in 190ns.
>>>>>>
>>>>>> Yes, that's what I modeled.  I see large current spikes on both
>>>>>> edges of
>>>>>> the pulse.  Regardless, I won't be using a discrete transistor.
>>>>>> I'll be
>>>>>> using the output from an FPGA.  Depending on the pulse width of the
>>>>>> output, the current in R2 is around 1 mA which is as much as the
>>>>>> entire
>>>>>> rest of the project.
>>>>>>
>>>>>> I can use a large resistor in series with the output into the cap and
>>>>>> drive it high and low for a range of duty cycles.  That will get me
>>>>>> what
>>>>>> I need.  This circuit only needs to source voltage, so I thought it
>>>>>> would use less current to only pull high.  We'll see what the real
>>>>>> circuit does when I use the actual FPGA output.  It doesn't have
>>>>>> to be
>>>>>> perfectly linear with duty cycle, but it does need to at least be
>>>>>> monotonic.
>>>>>
>>>>> Uh-huh, and what is the problem you can't simply drive this flea
>>>>> power RC from the FPGA directly? You do know how an RC works? Right?
>>>>
>>>> I'm not sure what you are talking about.  I will be driving the RC
>>>> directly from the FPGA output.
>>>>
>>>> I don't have FPGA outputs in the simulation, so I was using a FET as a
>>>> model.  Since it appears there are issues with charge injection when
>>>> driving a high impedance, I will just have to work that out on the
>>>> bench.
>>>
>>> Huh? You think that circuit is representative of an FPGA CMOS output?
>>> Don't think so...
>>
>> First order approximation, a FET.  I'm not going to try to model it more
>> closely.  There's not much I can do with it other than vary the drive
>> strenth/slew rate.  So as I said, I'll test it on the bench and see what
>> I can get out of it.
>>
>
> The FPGA CMOS output is likely to be push-pull, which will make a big
> difference.

Push-pull is just a pair of FETs, one pull up and one pull down.  There 
is also an enable so by setting the output low and toggling the enable, 
only one FET will be turned on and off.  This is very commonly done to 
make the output an open drain or by setting the output to a high and 
toggling the enable the output is an open source.

In FPGAs they normally also have multiple FETs in parallel to alter the 
drive strength.  So you can make it a stronger drive or a weaker drive 
although that can't be changed during operation, only by configuration. 
However, if you wish, you can wire multiple outputs in parallel with 
different drive strengths and in effect have a crude digital to current 
output of very low resolution and accuracy.  I never thought about this 
before but since each output can be high or low, a trinary code could be 
used.  I see drive strengths scaling by 1, 2 and 3.  So by combining 
three outputs of different strengths you could achieve sums of all 
integers from -6 to 6, 13 values.  Hmmmm...

-- 

Rick C

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#453338

On 24/03/2017 3:36 PM, rickman wrote:

> Push-pull is just a pair of FETs, one pull up and one pull down.  There
> is also an enable so by setting the output low and toggling the enable,
> only one FET will be turned on and off.  This is very commonly done to
> make the output an open drain or by setting the output to a high and
> toggling the enable the output is an open source.
>

The configuration avoids trying to get the gate charge through your load.

Sylvia.

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#452239

Well gee, it's a simulation, you don't even have to clip instruments onto 
the thing to see the current and voltage everywhere!

If you look at the V and I versus time, at the collector, you will see that 
Ic / (dVc/dt) is proportional to Ccb.  In other words, the transistor is 
off, and the capacitance is being charged through the 47k resistor.

Simple solution: remove the charge!

Connect collector directly to the load.  To set charge current, shove a 
resistor between +V and emitter.

Now you have a transconductance stage: voltage in, current out.  Or, with a 
resistor from +V to base, a current mirror (current in, current out).  Or a 
diode-strapped transistor plus a resistor (same thing, less drift and 
offset).

You still get some charge injection because of the base voltage moving 
(because it's Ccb, not just C to +V).  This can be reduced by using a 
relatively small emitter resistor (for, say, 0.1mA output, you only need to 
tug on the base by 0.1V, if you use a 1k resistor).  Or it can be isolated 
by cascoding the collector current with a second transistor (whose base 
voltage is fixed somewhat below the lowest base voltage you want to use on 
the first transistor).

HTH,

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com


"rickman" <gnuarm@gmail.com> wrote in message 
news:oaf7ro$efu$1@dont-email.me...
> I'm running a simulation where I'm pumping charge into a capacitor to 
> generate a voltage.  A transistor emitter/source is connected to the 
> positive rail and the collector/drain is connected to a 1 nF cap through a 
> 47k resistor.  When the base/gate is driven high to shut off the current I 
> see the current go up initially then taking almost 2 us to shut off.  I've 
> tried 2N3906 and BSS84 and a couple others selected randomly.  The 
> switching period is around 8 uS.
>
> Is this from the parasitic capacitance in the transistor?  The BSS84 only 
> has 1 nC gate charge and still the effect is very pronounced.
>
> Is there a way to mitigate this effect other than using a larger cap and 
> smaller resistors?
>
> -- 
>
> Rick C 

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#452244

On 3/17/2017 2:42 AM, Tim Williams wrote:
> Well gee, it's a simulation, you don't even have to clip instruments
> onto the thing to see the current and voltage everywhere!
>
> If you look at the V and I versus time, at the collector, you will see
> that Ic / (dVc/dt) is proportional to Ccb.  In other words, the
> transistor is off, and the capacitance is being charged through the 47k
> resistor.

Isn't that what I said, its the gate-drain charge?


> Simple solution: remove the charge!
>
> Connect collector directly to the load.  To set charge current, shove a
> resistor between +V and emitter.
>
> Now you have a transconductance stage: voltage in, current out.  Or,
> with a resistor from +V to base, a current mirror (current in, current
> out).  Or a diode-strapped transistor plus a resistor (same thing, less
> drift and offset).
>
> You still get some charge injection because of the base voltage moving
> (because it's Ccb, not just C to +V).  This can be reduced by using a
> relatively small emitter resistor (for, say, 0.1mA output, you only need
> to tug on the base by 0.1V, if you use a 1k resistor).  Or it can be
> isolated by cascoding the collector current with a second transistor
> (whose base voltage is fixed somewhat below the lowest base voltage you
> want to use on the first transistor).

Thanks for the info.  I'm not actually building a circuit from 
discretes.  So I'll just use a voltage source to model this for now and 
check it on the bench.

-- 

Rick C

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#452264

On 03/16/2017 07:44 PM, rickman wrote:
> I'm running a simulation where I'm pumping charge into a capacitor to
> generate a voltage.  A transistor emitter/source is connected to the
> positive rail and the collector/drain is connected to a 1 nF cap through
> a 47k resistor.  When the base/gate is driven high to shut off the
> current I see the current go up initially then taking almost 2 us to
> shut off.  I've tried 2N3906 and BSS84 and a couple others selected
> randomly.  The switching period is around 8 uS.
>
> Is this from the parasitic capacitance in the transistor?  The BSS84
> only has 1 nC gate charge and still the effect is very pronounced.
>
> Is there a way to mitigate this effect other than using a larger cap and
> smaller resistors?
>

A nanocoulomb in a microsecond is a milliamp.

How about an ATF55143 ePHEMT?

Cheers

Phil Hobbs

-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

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#452307

On Fri, 17 Mar 2017 09:53:17 -0400, Phil Hobbs wrote:

> A nanocoulomb in a microsecond is a milliamp.
> 
> How about an ATF55143 ePHEMT?

Cue J.L.

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