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Groups > sci.electronics.design > #452414
| Newsgroups | sci.electronics.design |
|---|---|
| Date | 2017-03-18 06:33 -0700 |
| References | (2 earlier) <oafka4$5on$1@dont-email.me> <ej14q3Fov9nU1@mid.individual.net> <oafq75$ivg$1@dont-email.me> <233f6753-c433-4b87-8650-8fb9f1a096cc@googlegroups.com> <oaivdi$96h$1@dont-email.me> |
| Message-ID | <199ff0ca-9852-411c-966b-c5efcaaaec6e@googlegroups.com> (permalink) |
| Subject | Re: Parasitics? |
| From | bloggs.fredbloggs.fred@gmail.com |
On Saturday, March 18, 2017 at 5:45:07 AM UTC-4, rickman wrote: > On 3/18/2017 4:36 AM, bloggs.fredbloggs.fred@gmail.com wrote: > > On Friday, March 17, 2017 at 12:57:57 AM UTC-4, rickman wrote: > >> On 3/16/2017 11:51 PM, Sylvia Else wrote: > >>> On 17/03/2017 2:16 PM, rickman wrote: > >>>> On 3/16/2017 9:21 PM, Sylvia Else wrote: > >>>>> On 17/03/2017 10:44 AM, rickman wrote: > >>>>>> I'm running a simulation where I'm pumping charge into a capacitor to > >>>>>> generate a voltage. A transistor emitter/source is connected to the > >>>>>> positive rail and the collector/drain is connected to a 1 nF cap > >>>>>> through > >>>>>> a 47k resistor. When the base/gate is driven high to shut off the > >>>>>> current I see the current go up initially then taking almost 2 us to > >>>>>> shut off. I've tried 2N3906 and BSS84 and a couple others selected > >>>>>> randomly. The switching period is around 8 uS. > >>>>>> > >>>>>> Is this from the parasitic capacitance in the transistor? The BSS84 > >>>>>> only has 1 nC gate charge and still the effect is very pronounced. > >>>>>> > >>>>>> Is there a way to mitigate this effect other than using a larger cap > >>>>>> and > >>>>>> smaller resistors? > >>>>>> > >>>>> When you try to drive the gate high, the gate-drain capacitance has to > >>>>> be charged, and the only way than can happen is for current to flow > >>>>> through R3. A back of the envelope calculation suggests that will take > >>>>> about the time you're seeing. > >>>>> > >>>>> To get it to switch more quickly, you need to reduce R3, or provide some > >>>>> other path for the current. > >>>>> > >>>>> A diode in series with R3, and a 1K resistor from the drain to ground > >>>>> improves things substantially. > >>>> > >>>> That actually makes things worse by substituting the capacitance of the > >>>> diode through the 1k resistor for the capacitance of the transistor. > >>>> > >>>> I was trying to use a very low power approach by injecting charge onto a > >>>> capacitor which would have a very low drain from it. But if low value > >>>> resistors have to be added, I can just use a dithered pullup/pulldown > >>>> instead. That may also have current injection, but it should be > >>>> approximately equal in both directions because of the push-pull output. > >>>> > >>> > >>> I had in mind this. The current through R3 reverses, then returns to > >>> zero in 190ns. > >> > >> Yes, that's what I modeled. I see large current spikes on both edges of > >> the pulse. Regardless, I won't be using a discrete transistor. I'll be > >> using the output from an FPGA. Depending on the pulse width of the > >> output, the current in R2 is around 1 mA which is as much as the entire > >> rest of the project. > >> > >> I can use a large resistor in series with the output into the cap and > >> drive it high and low for a range of duty cycles. That will get me what > >> I need. This circuit only needs to source voltage, so I thought it > >> would use less current to only pull high. We'll see what the real > >> circuit does when I use the actual FPGA output. It doesn't have to be > >> perfectly linear with duty cycle, but it does need to at least be > >> monotonic. > > > > Uh-huh, and what is the problem you can't simply drive this flea power RC from the FPGA directly? You do know how an RC works? Right? > > I'm not sure what you are talking about. I will be driving the RC > directly from the FPGA output. > > I don't have FPGA outputs in the simulation, so I was using a FET as a > model. Since it appears there are issues with charge injection when > driving a high impedance, I will just have to work that out on the bench. Huh? You think that circuit is representative of an FPGA CMOS output? Don't think so... > > -- > > Rick C
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Parasitics? rickman <gnuarm@gmail.com> - 2017-03-16 19:44 -0400
Re: Parasitics? bloggs.fredbloggs.fred@gmail.com - 2017-03-16 16:48 -0700
Re: Parasitics? Sylvia Else <sylvia@not.at.this.address> - 2017-03-17 10:59 +1100
Re: Parasitics? rickman <gnuarm@gmail.com> - 2017-03-16 20:19 -0400
Re: Parasitics? Sylvia Else <sylvia@not.at.this.address> - 2017-03-17 12:21 +1100
Re: Parasitics? rickman <gnuarm@gmail.com> - 2017-03-16 23:16 -0400
Re: Parasitics? Sylvia Else <sylvia@not.at.this.address> - 2017-03-17 14:51 +1100
Re: Parasitics? rickman <gnuarm@gmail.com> - 2017-03-17 00:57 -0400
Re: Parasitics? bloggs.fredbloggs.fred@gmail.com - 2017-03-18 01:36 -0700
Re: Parasitics? rickman <gnuarm@gmail.com> - 2017-03-18 05:45 -0400
Re: Parasitics? bloggs.fredbloggs.fred@gmail.com - 2017-03-18 06:33 -0700
Re: Parasitics? rickman <gnuarm@gmail.com> - 2017-03-18 12:22 -0400
Re: Parasitics? Sylvia Else <sylvia@not.at.this.address> - 2017-03-24 13:30 +1100
Re: Parasitics? rickman <gnuarm@gmail.com> - 2017-03-24 00:36 -0400
Re: Parasitics? Sylvia Else <sylvia@not.at.this.address> - 2017-03-24 16:10 +1100
Re: Parasitics? "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-17 01:42 -0500
Re: Parasitics? rickman <gnuarm@gmail.com> - 2017-03-17 04:11 -0400
Re: Parasitics? Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> - 2017-03-17 09:53 -0400
Re: Parasitics? Cursitor Doom <curd@notformail.com> - 2017-03-17 18:52 +0000
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