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Groups > linux.kernel > #1659597
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v2 07/11] drm: sun4i: add support for the TV encoder in H3 SoC |
| Date | 2017-06-07 11:40 +0200 |
| Message-ID | <tPFBw-4Pg-25@gated-at.bofh.it> (permalink) |
| References | <tOGgh-7tg-5@gated-at.bofh.it> <tOGpX-7x8-7@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
[Multipart message — attachments visible in raw view] - view raw
On Mon, Jun 05, 2017 at 12:01:45AM +0800, Icenowy Zheng wrote:
> Allwinner H3 features a TV encoder similar to the one in earlier SoCs,
> but has a internal fixed clock divider that divides the TCON1 clock
> (called TVE clock in datasheet) by 11.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> Changes in v2:
> - Quirk part rewritten.
>
> drivers/gpu/drm/sun4i/sun4i_tv.c | 35 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
> index 338b9e5bb2a3..b9ff6d5ea67a 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_tv.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
> @@ -13,6 +13,7 @@
> #include <linux/clk.h>
> #include <linux/component.h>
> #include <linux/of_address.h>
> +#include <linux/of_device.h>
> #include <linux/regmap.h>
> #include <linux/reset.h>
>
> @@ -169,14 +170,21 @@ struct tv_mode {
> const struct resync_parameters *resync_params;
> };
>
> +struct sun4i_tv_quirks {
> + int fixed_divider;
> +};
> +
> struct sun4i_tv {
> struct drm_connector connector;
> struct drm_encoder encoder;
>
> struct clk *clk;
> + struct clk *mod_clk;
> struct regmap *regs;
> struct reset_control *reset;
>
> + const struct sun4i_tv_quirks *quirks;
> +
> struct sun4i_drv *drv;
> };
>
> @@ -391,6 +399,12 @@ static void sun4i_tv_mode_set(struct drm_encoder *encoder,
> struct sun4i_tcon *tcon = crtc->tcon;
> const struct tv_mode *tv_mode = sun4i_tv_find_tv_by_mode(mode);
>
> + if (tv->quirks->fixed_divider) {
> + DRM_DEBUG_DRIVER("Applying fixed divider %d on TVE clock\n",
> + tv->quirks->fixed_divider);
> + mode->crtc_clock *= tv->quirks->fixed_divider;
> + }
> +
You're not allowed to change the mode in mode_set, and you shouldn't
even change it. The output pixel clock is still 27MHz.
You should implement that using the states, as we discussed already.
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread
[PATCH v2 00/11] Support for H3 Composite Output support Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:10 +0200
[PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:10 +0200
Re: [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Jernej Škrabec <jernej.skrabec@siol.net> - 2017-06-04 21:00 +0200
Re: [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 21:10 +0200
Re: [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-06-07 11:50 +0200
Re: [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Icenowy Zheng <icenowy@aosc.io> - 2017-06-07 13:20 +0200
Re: [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Icenowy Zheng <icenowy@aosc.io> - 2017-06-07 14:20 +0200
Re: [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Icenowy Zheng <icenowy@aosc.io> - 2017-06-07 16:30 +0200
Re: [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-06-09 17:00 +0200
Re: [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-06-07 16:50 +0200
[PATCH v2 11/11] [DO NOT MERGE] ARM: sun8i: h3: enable TV output on Orange Pi PC Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:10 +0200
[PATCH v2 05/11] drm: sun4i: add compatible for H3 display engine Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:20 +0200
[PATCH v2 06/11] drm: sun4i: add color space correction support for DE2 mixer Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:20 +0200
[PATCH v2 08/11] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3 Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:20 +0200
[PATCH v2 07/11] drm: sun4i: add support for the TV encoder in H3 SoC Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:20 +0200
Re: [PATCH v2 07/11] drm: sun4i: add support for the TV encoder in H3 SoC Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-06-07 11:40 +0200
Re: [PATCH v2 07/11] drm: sun4i: add support for the TV encoder in H3 SoC icenowy@aosc.io - 2017-06-11 08:50 +0200
Re: [PATCH v2 07/11] drm: sun4i: add support for the TV encoder in H3 SoC Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-06-13 09:50 +0200
Re: [PATCH v2 07/11] drm: sun4i: add support for the TV encoder in H3 SoC Icenowy Zheng <icenowy@aosc.io> - 2017-06-13 12:00 +0200
[PATCH v2 09/11] clk: sunxi-ng: export CLK_PLL_DE for H3 Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:20 +0200
[PATCH v2 02/11] drm: sun4i: add support for H3 mixers Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:30 +0200
[PATCH v2 10/11] ARM: sun8i: h3: add display engine pipeline for TVE Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:30 +0200
Re: [PATCH v2 10/11] ARM: sun8i: h3: add display engine pipeline for TVE Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-06-07 11:50 +0200
Re: [linux-sunxi] Re: [PATCH v2 10/11] ARM: sun8i: h3: add display engine pipeline for TVE icenowy@aosc.io - 2017-06-11 09:00 +0200
Re: [linux-sunxi] Re: [PATCH v2 10/11] ARM: sun8i: h3: add display engine pipeline for TVE Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-06-13 10:10 +0200
Re: [PATCH v2 00/11] Support for H3 Composite Output support icenowy@aosc.io - 2017-06-07 02:30 +0200
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