[PATCH v2 08/11] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3

From	Icenowy Zheng <icenowy@aosc.io>
Newsgroups	linux.kernel
Subject	[PATCH v2 08/11] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3
Date	2017-06-04 18:20 +0200
Message-ID	<tOGpX-7x8-3@gated-at.bofh.it> (permalink)
References	<tOGgh-7tg-5@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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Allwinner H3 features a PLL named CLK_PLL_DE, and a mod clock for the
"Display Engine 2.0" named CLK_DE. As the name indicated, the CLK_PLL_DE
is a PLL for CLK_DE.

Only CLK_DE and CLK_TVE have a parent of CLK_PLL_DE, and CLK_TVE is also
one part of the display clocks.

So allow CLK_DE to set CLK_PLL_DE (add CLK_SET_RATE_PARENT to it).

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 62e4f0d2b2fc..b6a1636c2f6b 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -439,7 +439,7 @@ static SUNXI_CCU_GATE(dram_ts_clk,	"dram-ts",	"dram",
 
 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
-				 0x104, 0, 4, 24, 3, BIT(31), 0);
+				 0x104, 0, 4, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
 
 static const char * const tcon_parents[] = { "pll-video" };
 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
-- 
2.12.2

Thread

[PATCH v2 00/11] Support for H3 Composite Output support Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:10 +0200
  [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:10 +0200
    Re: [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Jernej Škrabec <jernej.skrabec@siol.net> - 2017-06-04 21:00 +0200
      Re: [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 21:10 +0200
        Re: [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-06-07 11:50 +0200
          Re: [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Icenowy Zheng <icenowy@aosc.io> - 2017-06-07 13:20 +0200
          Re: [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Icenowy Zheng <icenowy@aosc.io> - 2017-06-07 14:20 +0200
            Re: [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Icenowy Zheng <icenowy@aosc.io> - 2017-06-07 16:30 +0200
            Re: [PATCH v2 04/11] drm: sun4i: add support for H3's TCON0/1 Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-06-07 16:50 +0200
  [PATCH v2 11/11] [DO NOT MERGE] ARM: sun8i: h3: enable TV output on Orange Pi PC Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:10 +0200
  [PATCH v2 05/11] drm: sun4i: add compatible for H3 display engine Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:20 +0200
  [PATCH v2 06/11] drm: sun4i: add color space correction support for DE2 mixer Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:20 +0200
  [PATCH v2 08/11] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3 Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:20 +0200
  [PATCH v2 07/11] drm: sun4i: add support for the TV encoder in H3 SoC Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:20 +0200
    Re: [PATCH v2 07/11] drm: sun4i: add support for the TV encoder in  H3 SoC Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-06-07 11:40 +0200
  [PATCH v2 09/11] clk: sunxi-ng: export CLK_PLL_DE for H3 Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:20 +0200
  [PATCH v2 02/11] drm: sun4i: add support for H3 mixers Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:30 +0200
  [PATCH v2 10/11] ARM: sun8i: h3: add display engine pipeline for TVE Icenowy Zheng <icenowy@aosc.io> - 2017-06-04 18:30 +0200
    Re: [PATCH v2 10/11] ARM: sun8i: h3: add display engine pipeline for  TVE Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-06-07 11:50 +0200
  Re: [PATCH v2 00/11] Support for H3 Composite Output support icenowy@aosc.io - 2017-06-07 02:30 +0200

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