RE: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot

From	Thomas Gleixner <tglx@linutronix.de>
Newsgroups	linux.kernel
Subject	RE: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot
Date	2016-10-27 20:30 +0200
Message-ID	<swXB7-5us-19@gated-at.bofh.it> (permalink)
References	<swTxv-2VB-3@gated-at.bofh.it> <swTxx-2VB-55@gated-at.bofh.it> <swUad-3cE-1@gated-at.bofh.it> <swWc2-4su-19@gated-at.bofh.it>
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On Thu, 27 Oct 2016, Andrejczuk, Grzegorz wrote:
> > >  	init_intel_energy_perf(c);
> > > +
> > > +	/*
> > > +	* Setting ring 3 MONITOR/MWAIT for thread
> > > +	* when CPU is Xeon Phi Family x200 (KnightsLanding).
> > > +	*/
> > > +	if (c->x86 == 6 && c->x86_model == INTEL_FAM6_XEON_PHI_KNL)
> >
> > Please move this conditional into the probe function.
> >
> > > +		probe_xeon_phi_r3mwait(c);
> >
> > Can you please check with your hardware people, whether this function
> > is somewhere detectable. bit 0 of the MISC_*FEATURE* MSR (Ring 3 CPUID
> > fault enable) is detectable via the PLATFORM_INFO MSR. I would be
> > surprised if this thing is not detectable in some way.
> >
> > I really prefer detectable things over hardcoded crap which depends on
> > model information.
>
> I asked hardware people and MSR 0x140 should be called
> MSR_MISC_FEATURE_ENABLES and there is no other feature MSR indicating
> that this bit can be set.  Unfortunately hardcoded crap has to be used.

Can you please tell your hardware folks, that non discoverable features are
a horror? We really need unique detection of features across all the
various cpu platforms. Making stuff depend on models, stepping results in a
nightmare.

Thanks,

	tglx

Thread

[PATCH v6 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-27 16:10 +0200
  [PATCH v6: 4/4] x86/cpufeature: Add R3MWAIT to CPU features Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-27 16:10 +0200
    Re: [PATCH v6: 4/4] x86/cpufeature: Add R3MWAIT to CPU features Borislav Petkov <bp@suse.de> - 2016-10-27 16:40 +0200
      RE: [PATCH v6: 4/4] x86/cpufeature: Add R3MWAIT to CPU features "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com> - 2016-10-27 18:50 +0200
        Re: [PATCH v6: 4/4] x86/cpufeature: Add R3MWAIT to CPU features Borislav Petkov <bp@suse.de> - 2016-10-27 19:10 +0200
  [PATCH v6: 1/4] x86/msr: Add R3MWAIT register and bit to msr-info.h Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-27 16:10 +0200
    Re: [PATCH v6: 1/4] x86/msr: Add R3MWAIT register and bit to  msr-info.h Thomas Gleixner <tglx@linutronix.de> - 2016-10-27 16:40 +0200
  [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-27 16:10 +0200
    Re: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot Thomas Gleixner <tglx@linutronix.de> - 2016-10-27 16:50 +0200
      RE: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com> - 2016-10-27 19:00 +0200
        RE: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot Thomas Gleixner <tglx@linutronix.de> - 2016-10-27 20:30 +0200
  [PATCH v6: 3/4] x86: Use HWCAP2 to expose Xeon Phi ring 3 MWAIT Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-27 16:10 +0200

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