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[PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot

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If processor is Intel Xeon Phi x200 we enable user-level mwait feature.
Enabling this feature suppresses invalid-opcode error, when MONITOR/MWAIT
is called from ring 3.

Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
 Documentation/kernel-parameters.txt |  5 +++++
 arch/x86/kernel/cpu/intel.c         | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index a4f4d69..d58915b 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -3120,6 +3120,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 	pg.		[PARIDE]
 			See Documentation/blockdev/paride.txt.
 
+	phir3mwait=	[X86] Disable Intel Xeon Phi x200 ring 3 MONITOR/MWAIT
+			feature for all cpus.
+			Format: { disable }
+			See arch/x86/kernel/cpu/intel.c
+
 	pirq=		[SMP,APIC] Manual mp-table setup
 			See Documentation/x86/i386/IO-APIC.txt.
 
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index fcd484d..2140ed3 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -61,6 +61,36 @@ void check_mpx_erratum(struct cpuinfo_x86 *c)
 	}
 }
 
+#ifdef CONFIG_X86_64
+static int phi_r3mwait_disabled __read_mostly;
+
+static int __init phir3mwait_disable(char *__unused)
+{
+	phi_r3mwait_disabled = 1;
+	pr_warn("x86/phir3mwait: Disabled ring 3 MWAIT for Xeon Phi");
+	return 1;
+}
+__setup("phir3mwait=disable", phir3mwait_disable);
+
+static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
+{
+	u64 msr;
+
+	rdmsrl(MSR_PHI_MISC_THD_FEATURE, msr);
+
+	if (phi_r3mwait_disabled) {
+		msr &= ~MSR_PHI_MISC_THD_FEATURE_R3MWAIT;
+		wrmsrl(MSR_PHI_MISC_THD_FEATURE, msr);
+	} else {
+		msr |= MSR_PHI_MISC_THD_FEATURE_R3MWAIT;
+		wrmsrl(MSR_PHI_MISC_THD_FEATURE, msr);
+	}
+}
+
+#else
+static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *__unused) {}
+#endif
+
 static void early_init_intel(struct cpuinfo_x86 *c)
 {
 	u64 misc_enable;
@@ -565,6 +595,13 @@ static void init_intel(struct cpuinfo_x86 *c)
 		detect_vmx_virtcap(c);
 
 	init_intel_energy_perf(c);
+
+	/*
+	* Setting ring 3 MONITOR/MWAIT for thread
+	* when CPU is Xeon Phi Family x200 (KnightsLanding).
+	*/
+	if (c->x86 == 6 && c->x86_model == INTEL_FAM6_XEON_PHI_KNL)
+		probe_xeon_phi_r3mwait(c);
 }
 
 #ifdef CONFIG_X86_32
-- 
2.5.1

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[PATCH v6 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-27 16:10 +0200
  [PATCH v6: 4/4] x86/cpufeature: Add R3MWAIT to CPU features Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-27 16:10 +0200
    Re: [PATCH v6: 4/4] x86/cpufeature: Add R3MWAIT to CPU features Borislav Petkov <bp@suse.de> - 2016-10-27 16:40 +0200
      RE: [PATCH v6: 4/4] x86/cpufeature: Add R3MWAIT to CPU features "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com> - 2016-10-27 18:50 +0200
        Re: [PATCH v6: 4/4] x86/cpufeature: Add R3MWAIT to CPU features Borislav Petkov <bp@suse.de> - 2016-10-27 19:10 +0200
  [PATCH v6: 1/4] x86/msr: Add R3MWAIT register and bit to msr-info.h Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-27 16:10 +0200
    Re: [PATCH v6: 1/4] x86/msr: Add R3MWAIT register and bit to  msr-info.h Thomas Gleixner <tglx@linutronix.de> - 2016-10-27 16:40 +0200
  [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-27 16:10 +0200
    Re: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot Thomas Gleixner <tglx@linutronix.de> - 2016-10-27 16:50 +0200
      RE: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com> - 2016-10-27 19:00 +0200
        RE: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot Thomas Gleixner <tglx@linutronix.de> - 2016-10-27 20:30 +0200
  [PATCH v6: 3/4] x86: Use HWCAP2 to expose Xeon Phi ring 3 MWAIT Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-27 16:10 +0200

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