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Groups > linux.kernel > #1510199
| From | Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v6: 4/4] x86/cpufeature: Add R3MWAIT to CPU features |
| Date | 2016-10-27 16:10 +0200 |
| Message-ID | <swTxw-2VB-5@gated-at.bofh.it> (permalink) |
| References | <swTxv-2VB-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Add cpu feature for ring 3 monitor/mwait.
Set HWCAP2 1st bit during init.
Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
arch/x86/include/asm/cpufeatures.h | 2 ++
arch/x86/kernel/cpu/intel.c | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 92a8308..d430200 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -71,6 +71,8 @@
#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */
#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */
#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */
+/* Xeon Phi x200 ring 3 MONITOR/MWAIT enabled */
+#define X86_FEATURE_PHIR3MWAIT ( 2*32+ 4)
/* Other features, Linux-defined mapping, word 3 */
/* This range is used for feature bits which conflict or are synthesized */
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 2140ed3..3f02c7e 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -14,6 +14,8 @@
#include <asm/bugs.h>
#include <asm/cpu.h>
#include <asm/intel-family.h>
+#include <asm/hwcap2.h>
+#include <asm/elf.h>
#ifdef CONFIG_X86_64
#include <linux/topology.h>
@@ -84,6 +86,8 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
} else {
msr |= MSR_PHI_MISC_THD_FEATURE_R3MWAIT;
wrmsrl(MSR_PHI_MISC_THD_FEATURE, msr);
+ set_cpu_cap(c, X86_FEATURE_PHIR3MWAIT);
+ ELF_HWCAP2 |= HWCAP2_PHIR3MWAIT;
}
}
--
2.5.1
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[PATCH v6 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-27 16:10 +0200
[PATCH v6: 4/4] x86/cpufeature: Add R3MWAIT to CPU features Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-27 16:10 +0200
Re: [PATCH v6: 4/4] x86/cpufeature: Add R3MWAIT to CPU features Borislav Petkov <bp@suse.de> - 2016-10-27 16:40 +0200
RE: [PATCH v6: 4/4] x86/cpufeature: Add R3MWAIT to CPU features "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com> - 2016-10-27 18:50 +0200
Re: [PATCH v6: 4/4] x86/cpufeature: Add R3MWAIT to CPU features Borislav Petkov <bp@suse.de> - 2016-10-27 19:10 +0200
[PATCH v6: 1/4] x86/msr: Add R3MWAIT register and bit to msr-info.h Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-27 16:10 +0200
Re: [PATCH v6: 1/4] x86/msr: Add R3MWAIT register and bit to msr-info.h Thomas Gleixner <tglx@linutronix.de> - 2016-10-27 16:40 +0200
[PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-27 16:10 +0200
Re: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot Thomas Gleixner <tglx@linutronix.de> - 2016-10-27 16:50 +0200
RE: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com> - 2016-10-27 19:00 +0200
RE: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot Thomas Gleixner <tglx@linutronix.de> - 2016-10-27 20:30 +0200
[PATCH v6: 3/4] x86: Use HWCAP2 to expose Xeon Phi ring 3 MWAIT Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-27 16:10 +0200
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