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Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier

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On 31/08/16 15:28, Peter Zijlstra wrote:
> On Wed, Aug 31, 2016 at 02:36:26PM +0100, Matt Redfearn wrote:
>> The code previously had 0x10 as a magic number, this patch just replaces
>> that with a #defined name. The value is documented in the MIPS64 instruction
>> set manual, https://imgtec.com/?do-download=4302, table 6.5.
>>
>> This sync type has been standard since MIPSr2. That document also states
>> that "If an implementation does not use one of these non-zero values to
>> define a different synchronization behavior, then that non-zero value of
>> stype must act the same as stype zero completion barrier." As such,
>> stype_ordering can always be set to this sync type rather than setting it
>> only for certain CPUs.

Hi Peter,

> Right. We all had a bunch of fun trying to decode that manual a while
> back, and IIRC were left with a bunch of questions on what it all meant
> in 3+ CPU scenarios.

Yes, I remember that fun....

>
> In anycase, not sure why I was Cc'ed to this patch, but in general I

Patman decided to CC you as you've touched arch/mips/include/barrier.h I 
suppose.

> have low confidence in barrier patches that lack lots of detail. And the
> code in question has woefully inadequate comments:
>
>                  /* Ordering barrier */
>                  uasm_i_sync(&p, stype_ordering);
>
> Order what against what and why? Is my first question. A comment really
> should explain.

Fair enough - we'll put something together to improve the comments.

>
> In any case, you've removed the only (runtime) assignment to the
> variable, it can become 'const'.

True enough.

Thanks,
Matt

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[PATCH 00/10] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 05/10] MIPS: pm-cps: Add P6600 implementation lightweight sync types Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 09/10] MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 10/10] cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs. Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 03/10] MIPS: pm-cps: Change FSB workaround to CPU blacklist Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 02/10] MIPS: CPC: Avoid lock when MIPS CM >= 3 is present Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 08/10] MIPS: pm-cps: Support CM3 changes to Coherence Enable Register Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
    Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight  ordering barrier Peter Zijlstra <peterz@infradead.org> - 2016-08-31 13:50 +0200
      Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight  ordering barrier Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 15:40 +0200
        Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight  ordering barrier Peter Zijlstra <peterz@infradead.org> - 2016-08-31 16:30 +0200
          Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight  ordering barrier Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 17:50 +0200
  [PATCH 04/10] MIPS: pm-cps: Remove I6400 sync types Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 07/10] MIPS: pm-cps: Add MIPSr6 CPU support Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200

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