Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1473291
| From | Matt Redfearn <matt.redfearn@imgtec.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 05/10] MIPS: pm-cps: Add P6600 implementation lightweight sync types |
| Date | 2016-08-31 12:50 +0200 |
| Message-ID | <scbfH-1kx-15@gated-at.bofh.it> (permalink) |
| References | <scbfH-1kx-7@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
P6600 implements the same lightweight sync types as previous CPUs. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> --- arch/mips/kernel/pm-cps.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c index c6b9ad2256f0..f8c8edd0a451 100644 --- a/arch/mips/kernel/pm-cps.c +++ b/arch/mips/kernel/pm-cps.c @@ -674,6 +674,7 @@ static int __init cps_pm_init(void) case CPU_PROAPTIV: case CPU_M5150: case CPU_P5600: + case CPU_P6600: stype_intervention = 0x2; stype_memory = 0x3; stype_ordering = 0x10; -- 2.7.4
Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread
[PATCH 00/10] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 05/10] MIPS: pm-cps: Add P6600 implementation lightweight sync types Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 09/10] MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 10/10] cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs. Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 03/10] MIPS: pm-cps: Change FSB workaround to CPU blacklist Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 02/10] MIPS: CPC: Avoid lock when MIPS CM >= 3 is present Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 08/10] MIPS: pm-cps: Support CM3 changes to Coherence Enable Register Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Peter Zijlstra <peterz@infradead.org> - 2016-08-31 13:50 +0200
Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 15:40 +0200
Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Peter Zijlstra <peterz@infradead.org> - 2016-08-31 16:30 +0200
Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 17:50 +0200
[PATCH 04/10] MIPS: pm-cps: Remove I6400 sync types Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 07/10] MIPS: pm-cps: Add MIPSr6 CPU support Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
csiph-web