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Groups > linux.kernel > #1473293
| From | Matt Redfearn <matt.redfearn@imgtec.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 09/10] MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other |
| Date | 2016-08-31 12:50 +0200 |
| Message-ID | <scbfI-1kx-41@gated-at.bofh.it> (permalink) |
| References | <scbfH-1kx-7@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
All calls to mips_cpc_lock_other should be wrapped in
mips_cm_lock_other. This only matters if the system has CM3 and is using
cpu idle, since otherwise a) the CPC lock is sufficent for CM < 3 and b)
any systems with CM > 3 have not been able to use cpu idle until now.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
---
arch/mips/kernel/smp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index f95f094f36e4..78ccd5388654 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -192,9 +192,11 @@ void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
continue;
while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
+ mips_cm_lock_other(core, 0);
mips_cpc_lock_other(core);
write_cpc_co_cmd(CPC_Cx_CMD_PWRUP);
mips_cpc_unlock_other();
+ mips_cm_unlock_other();
}
}
}
--
2.7.4
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[PATCH 00/10] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 05/10] MIPS: pm-cps: Add P6600 implementation lightweight sync types Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 09/10] MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 10/10] cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs. Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 03/10] MIPS: pm-cps: Change FSB workaround to CPU blacklist Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 02/10] MIPS: CPC: Avoid lock when MIPS CM >= 3 is present Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 08/10] MIPS: pm-cps: Support CM3 changes to Coherence Enable Register Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Peter Zijlstra <peterz@infradead.org> - 2016-08-31 13:50 +0200
Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 15:40 +0200
Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Peter Zijlstra <peterz@infradead.org> - 2016-08-31 16:30 +0200
Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 17:50 +0200
[PATCH 04/10] MIPS: pm-cps: Remove I6400 sync types Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
[PATCH 07/10] MIPS: pm-cps: Add MIPSr6 CPU support Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
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