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[PATCH 02/10] MIPS: CPC: Avoid lock when MIPS CM >= 3 is present

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MIPS CM version 3 removed the CPC_CL_OTHER register and instead the
CM_CL_OTHER register is used to redirect the CPC_OTHER region. As such,
we should not write the unimplmented register and can avoid the
spinlock as well.
These lock functions should aleady be called within the context of a
mips_cm_{lock,unlock}_other pair ensuring the correct CPC_OTHER region
will be accessed.

Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/kernel/mips-cpc.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c
index 0e337f55ac60..2a45867d3b4f 100644
--- a/arch/mips/kernel/mips-cpc.c
+++ b/arch/mips/kernel/mips-cpc.c
@@ -71,6 +71,11 @@ int mips_cpc_probe(void)
 void mips_cpc_lock_other(unsigned int core)
 {
 	unsigned int curr_core;
+
+	if (mips_cm_revision() >= CM_REV_CM3)
+		/* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
+		return;
+
 	preempt_disable();
 	curr_core = current_cpu_data.core;
 	spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
@@ -86,7 +91,13 @@ void mips_cpc_lock_other(unsigned int core)
 
 void mips_cpc_unlock_other(void)
 {
-	unsigned int curr_core = current_cpu_data.core;
+	unsigned int curr_core;
+
+	if (mips_cm_revision() >= CM_REV_CM3)
+		/* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
+		return;
+
+	curr_core = current_cpu_data.core;
 	spin_unlock_irqrestore(&per_cpu(cpc_core_lock, curr_core),
 			       per_cpu(cpc_core_lock_flags, curr_core));
 	preempt_enable();
-- 
2.7.4

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[PATCH 00/10] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 05/10] MIPS: pm-cps: Add P6600 implementation lightweight sync types Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 09/10] MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 10/10] cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs. Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 03/10] MIPS: pm-cps: Change FSB workaround to CPU blacklist Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 02/10] MIPS: CPC: Avoid lock when MIPS CM >= 3 is present Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 08/10] MIPS: pm-cps: Support CM3 changes to Coherence Enable Register Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
    Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight  ordering barrier Peter Zijlstra <peterz@infradead.org> - 2016-08-31 13:50 +0200
      Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight  ordering barrier Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 15:40 +0200
        Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight  ordering barrier Peter Zijlstra <peterz@infradead.org> - 2016-08-31 16:30 +0200
          Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight  ordering barrier Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 17:50 +0200
  [PATCH 04/10] MIPS: pm-cps: Remove I6400 sync types Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200
  [PATCH 07/10] MIPS: pm-cps: Add MIPSr6 CPU support Matt Redfearn <matt.redfearn@imgtec.com> - 2016-08-31 12:50 +0200

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