Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1402101

[PATCH v8 08/10] reset: mediatek: Add MT2701 reset driver

Show all headers | View raw

From: Shunli Wang <shunli.wang@mediatek.com>

In infrasys and perifsys, there are many reset
control bits for kinds of modules. These bits are
used as actual reset controllers to be registered
into kernel's generic reset controller framework.

Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Tested-by: John Crispin <blogic@openwrt.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 drivers/clk/mediatek/clk-mt2701-hif.c | 2 ++
 drivers/clk/mediatek/clk-mt2701.c     | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
index 3f6cea2..28014bf 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -55,6 +55,8 @@ static void mtk_hifsys_init(struct device_node *node)
 	if (r)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
+
+	mtk_register_reset_controller(node, 1, 0x34);
 }
 
 static const struct of_device_id of_match_clk_mt2701_hif[] = {
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 08a2954..b3cde20 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -791,6 +791,8 @@ static void mtk_infrasys_init(struct device_node *node)
 	if (r)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
+
+	mtk_register_reset_controller(node, 2, 0x30);
 }
 
 static const struct mtk_gate_regs peri0_cg_regs = {
@@ -911,6 +913,8 @@ static void mtk_pericfg_init(struct device_node *node)
 	if (r)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
+
+	mtk_register_reset_controller(node, 2, 0x0);
 }
 
 #define MT8590_PLL_FMAX		(2000 * MHZ)
-- 
1.9.1

Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread

Thread

[PATCH v8 0/10] Add clock support for Mediatek MT2701 Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200
  [PATCH v8 10/10] arm: dts: mt2701: Use real clock for UARTs Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200
  [PATCH v8 04/10] dt-bindings: ARM: Mediatek: Document bindings for MT2701 Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200
  [PATCH v8 08/10] reset: mediatek: Add MT2701 reset driver Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200
  [PATCH v8 09/10] arm: dts: mt2701: Add clock controller device nodes Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200
  [PATCH v8 05/10] clk: mediatek: Add dt-bindings for MT2701 clocks Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200
  [PATCH v8 01/10] clk: fix initial state of critical clock's parents Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200
  [PATCH v8 02/10] clk: mediatek: remove __init from clk registration functions Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200
  [PATCH v8 07/10] reset: mediatek: Add MT2701 reset controller dt-binding file Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:20 +0200
  [PATCH v8 03/10] clk: mediatek: Refine the makefile to support multiple clock drivers Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:20 +0200

csiph-web