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Groups > linux.kernel > #1402098
| From | Erin Lo <erin.lo@mediatek.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v8 10/10] arm: dts: mt2701: Use real clock for UARTs |
| Date | 2016-05-17 07:10 +0200 |
| Message-ID | <rzFqx-fn-9@gated-at.bofh.it> (permalink) |
| References | <rzFqx-fn-5@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
We used to use a fixed rate clock for the UARTs. Now that we have clock
support we can associate the correct clocks to the UARTs and drop the
26MHz fixed rate UART clock.
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
arch/arm/boot/dts/mt2701.dtsi | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 171d4da..e79e88f 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -71,12 +71,6 @@
#clock-cells = <0>;
};
- uart_clk: dummy26m {
- compatible = "fixed-clock";
- clock-frequency = <26000000>;
- #clock-cells = <0>;
- };
-
clk26m: oscillator@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -167,7 +161,8 @@
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
+ clock-names = "baud", "bus";
status = "disabled";
};
@@ -176,7 +171,8 @@
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
+ clock-names = "baud", "bus";
status = "disabled";
};
@@ -185,7 +181,8 @@
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
+ clock-names = "baud", "bus";
status = "disabled";
};
@@ -194,7 +191,8 @@
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
+ clock-names = "baud", "bus";
status = "disabled";
};
};
--
1.9.1
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[PATCH v8 0/10] Add clock support for Mediatek MT2701 Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200 [PATCH v8 10/10] arm: dts: mt2701: Use real clock for UARTs Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200 [PATCH v8 04/10] dt-bindings: ARM: Mediatek: Document bindings for MT2701 Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200 [PATCH v8 08/10] reset: mediatek: Add MT2701 reset driver Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200 [PATCH v8 09/10] arm: dts: mt2701: Add clock controller device nodes Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200 [PATCH v8 05/10] clk: mediatek: Add dt-bindings for MT2701 clocks Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200 [PATCH v8 01/10] clk: fix initial state of critical clock's parents Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200 [PATCH v8 02/10] clk: mediatek: remove __init from clk registration functions Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:10 +0200 [PATCH v8 07/10] reset: mediatek: Add MT2701 reset controller dt-binding file Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:20 +0200 [PATCH v8 03/10] clk: mediatek: Refine the makefile to support multiple clock drivers Erin Lo <erin.lo@mediatek.com> - 2016-05-17 07:20 +0200
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