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Groups > comp.lang.forth > #49442
| From | Paul Rubin <no.email@nospam.invalid> |
|---|---|
| Newsgroups | comp.lang.vhdl, comp.lang.forth |
| Subject | Re: Forth in VHDL |
| Date | 2016-07-24 22:38 -0700 |
| Organization | A noiseless patient Spider |
| Message-ID | <87fuqy9t02.fsf@jester.gateway.pace.com> (permalink) |
| References | (2 earlier) <nn3vln$lp9$2@dont-email.me> <nn40r6$o88$1@dont-email.me> <nn43co$tha$1@dont-email.me> <nn468n$3k2$1@dont-email.me> <nn47lq$6r4$1@dont-email.me> |
Cross-posted to 2 groups.
rickman <gnuarm@gmail.com> writes: > The speed advantage of async logic is essentially a myth in that you > have to design for real time needs which means deadlines. I thought the idea was instructions could have variable latency depending on the data, and async meant you could start the next instruction as soon as the previous one finished. > You really can't design async logic in FPGAs that I know of. It has > to be custom chips. Hmm, I wonder what the obstacle is. Certainly async was used in old discrete or low-integration machines like the PDP-6 and KA10 from the 1970s. I think it feel out of favor as machines got more complex, due to debugging headaches etc. > I looked at what amounts to VLIW for MISC processors That's sort of what the Novix was, I thought.
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Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 22:29 -0400
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 23:01 -0400
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 23:05 -0400
Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 22:25 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 00:08 -0400
Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 23:57 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 01:22 -0400
Re: Forth in VHDL Paul Rubin <no.email@nospam.invalid> - 2016-07-24 22:38 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 01:53 -0400
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 05:31 -0700
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 05:36 -0700
Re: Forth in VHDL Richard Owlett <rowlett@cloud85.net> - 2016-07-25 08:14 -0500
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 07:37 -0700
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 08:01 -0700
Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-25 14:11 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 17:39 -0400
Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-25 18:01 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 19:40 -0400
Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-26 11:04 +0100
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 11:13 -0400
Re: Forth in VHDL anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2016-07-26 16:00 +0000
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 12:58 -0400
Re: Forth in VHDL anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2016-07-27 09:39 +0000
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 10:01 -0400
Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-27 22:46 +0100
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-26 09:43 -0700
Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-28 09:12 +0100
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-28 05:04 -0400
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-28 07:56 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-28 13:04 -0400
Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-08-02 12:21 +0100
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-28 08:02 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 18:15 -0400
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-28 15:19 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-31 18:43 -0400
Re: Forth in VHDL Paul Rubin <no.email@nospam.invalid> - 2016-07-31 17:10 -0700
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-24 20:08 -0700
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-24 20:33 -0700
Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 22:58 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 00:17 -0400
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-25 10:02 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 14:13 -0400
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 14:17 -0400
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-25 15:04 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 19:28 -0400
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-25 17:20 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 23:07 -0400
Re: Forth in VHDL Andrew Haley <andrew29@littlepinkcloud.invalid> - 2016-07-26 03:07 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 13:05 -0400
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-26 16:22 -0700
Re: Forth in VHDL Andrew Haley <andrew29@littlepinkcloud.invalid> - 2016-07-27 03:57 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 10:34 -0400
Re: Forth in VHDL Andrew Haley <andrew29@littlepinkcloud.invalid> - 2016-07-27 11:15 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 12:51 -0400
Re: Forth in VHDL Andrew Haley <andrew29@littlepinkcloud.invalid> - 2016-07-27 16:12 -0500
Re: Forth in VHDL "Elizabeth D. Rather" <erather@forth.com> - 2016-07-27 12:43 -1000
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-28 00:40 -0400
Re: Forth in VHDL hughaguilar96@gmail.com - 2016-08-02 22:45 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-28 00:39 -0400
Re: Forth in VHDL wzab01@gmail.com - 2016-07-25 01:48 -0700
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 05:57 -0700
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 06:02 -0700
Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-30 16:40 +0100
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-08-01 08:58 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-31 17:10 -0400
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-08-01 09:02 -0700
Re: Forth in VHDL Ilya Tarasov <ilya74.tarasov@gmail.com> - 2016-07-29 05:42 -0700
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