Re: Forth in VHDL

From	Paul Rubin <no.email@nospam.invalid>
Newsgroups	comp.lang.vhdl, comp.lang.forth
Subject	Re: Forth in VHDL
Date	2016-07-24 22:38 -0700
Organization	A noiseless patient Spider
Message-ID	<87fuqy9t02.fsf@jester.gateway.pace.com> (permalink)
References	(2 earlier) <nn3vln$lp9$2@dont-email.me> <nn40r6$o88$1@dont-email.me> <nn43co$tha$1@dont-email.me> <nn468n$3k2$1@dont-email.me> <nn47lq$6r4$1@dont-email.me>

Cross-posted to 2 groups.

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rickman <gnuarm@gmail.com> writes:
> The speed advantage of async logic is essentially a myth in that you
> have to design for real time needs which means deadlines.  

I thought the idea was instructions could have variable latency
depending on the data, and async meant you could start the next
instruction as soon as the previous one finished.

> You really can't design async logic in FPGAs that I know of.  It has
> to be custom chips.

Hmm, I wonder what the obstacle is.  Certainly async was used in old
discrete or low-integration machines like the PDP-6 and KA10 from the
1970s.  I think it feel out of favor as machines got more complex, due
to debugging headaches etc.

> I looked at what amounts to VLIW for MISC processors

That's sort of what the Novix was, I thought.

Thread

Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 22:29 -0400
  Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 23:01 -0400
    Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 23:05 -0400
      Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 22:25 -0500
        Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 00:08 -0400
          Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 23:57 -0500
            Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 01:22 -0400
              Re: Forth in VHDL Paul Rubin <no.email@nospam.invalid> - 2016-07-24 22:38 -0700
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 01:53 -0400
              Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-25 14:11 -0500
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 17:39 -0400
                Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-25 18:01 -0500
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 19:40 -0400
                Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-26 11:04 +0100
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 11:13 -0400
                Re: Forth in VHDL anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2016-07-26 16:00 +0000
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 12:58 -0400
                Re: Forth in VHDL anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2016-07-27 09:39 +0000
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 10:01 -0400
                Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-27 22:46 +0100
    Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 18:15 -0400

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