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Groups > linux.kernel > #1574401
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 7/9] ARM: sun5i: a10s: Merge common controllers into the common DTSI |
| Date | 2017-02-06 08:10 +0100 |
| Message-ID | <t7LB1-1HH-23@gated-at.bofh.it> (permalink) |
| References | <t7LB0-1HH-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Some controllers found in the A10s DTSI actually apply to all of the sun5i
family. Move those into the common DTSI so that all SoCs can benefit from
it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 70 +--------------------------------
arch/arm/boot/dts/sun5i.dtsi | 62 ++++++++++++++++++++++++++++-
2 files changed, 62 insertions(+), 70 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 5122d1179e59..074485782a4a 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -70,45 +70,9 @@
<&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;
status = "disabled";
};
-
- framebuffer@0 {
- compatible = "allwinner,simple-framebuffer",
- "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0";
- clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
- status = "disabled";
- };
-
- framebuffer@1 {
- compatible = "allwinner,simple-framebuffer",
- "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0-tve0";
- clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
- <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
- status = "disabled";
- };
};
soc@01c00000 {
- emac: ethernet@01c0b000 {
- compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
- interrupts = <55>;
- clocks = <&ccu CLK_AHB_EMAC>;
- allwinner,sram = <&emac_sram 1>;
- status = "disabled";
- };
-
- mdio: mdio@01c0b080 {
- compatible = "allwinner,sun4i-a10-mdio";
- reg = <0x01c0b080 0x14>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
pwm: pwm@01c20e00 {
compatible = "allwinner,sun5i-a10s-pwm";
reg = <0x01c20e00 0xc>;
@@ -116,26 +80,6 @@
#pwm-cells = <3>;
status = "disabled";
};
-
- uart0: serial@01c28000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28000 0x400>;
- interrupts = <1>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_APB1_UART0>;
- status = "disabled";
- };
-
- uart2: serial@01c28800 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28800 0x400>;
- interrupts = <3>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_APB1_UART2>;
- status = "disabled";
- };
};
};
@@ -165,15 +109,6 @@
function = "emac";
};
- emac_pins_a: emac0@0 {
- pins = "PD6", "PD7", "PD10",
- "PD11", "PD12", "PD13", "PD14",
- "PD15", "PD18", "PD19", "PD20",
- "PD21", "PD22", "PD23", "PD24",
- "PD25", "PD26", "PD27";
- function = "emac";
- };
-
mmc1_pins_a: mmc1@0 {
pins = "PG3", "PG4", "PG5",
"PG6", "PG7", "PG8";
@@ -193,9 +128,4 @@
};
&sram_a {
- emac_sram: sram-section@8000 {
- compatible = "allwinner,sun4i-a10-sram-a3-a4";
- reg = <0x8000 0x4000>;
- status = "disabled";
- };
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index f27ca0be5835..9ba0c0302183 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -77,6 +77,16 @@
<&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
status = "disabled";
};
+
+ framebuffer@1 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0-tve0";
+ clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
+ <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+ <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
+ status = "disabled";
+ };
};
clocks {
@@ -120,6 +130,12 @@
ranges = <0 0x00000000 0xc000>;
};
+ emac_sram: sram-section@8000 {
+ compatible = "allwinner,sun4i-a10-sram-a3-a4";
+ reg = <0x8000 0x4000>;
+ status = "disabled";
+ };
+
sram_d: sram@00010000 {
compatible = "mmio-sram";
reg = <0x00010000 0x1000>;
@@ -171,6 +187,23 @@
#size-cells = <0>;
};
+ emac: ethernet@01c0b000 {
+ compatible = "allwinner,sun4i-a10-emac";
+ reg = <0x01c0b000 0x1000>;
+ interrupts = <55>;
+ clocks = <&ccu CLK_AHB_EMAC>;
+ allwinner,sram = <&emac_sram 1>;
+ status = "disabled";
+ };
+
+ mdio: mdio@01c0b080 {
+ compatible = "allwinner,sun4i-a10-mdio";
+ reg = <0x01c0b080 0x14>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
tcon0: lcd-controller@01c0c000 {
compatible = "allwinner,sun5i-a13-tcon";
reg = <0x01c0c000 0x1000>;
@@ -326,6 +359,15 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ emac_pins_a: emac0@0 {
+ pins = "PD6", "PD7", "PD10",
+ "PD11", "PD12", "PD13", "PD14",
+ "PD15", "PD18", "PD19", "PD20",
+ "PD21", "PD22", "PD23", "PD24",
+ "PD25", "PD26", "PD27";
+ function = "emac";
+ };
+
i2c0_pins_a: i2c0@0 {
pins = "PB0", "PB1";
function = "i2c0";
@@ -472,6 +514,16 @@
#thermal-sensor-cells = <0>;
};
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <1>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_APB1_UART0>;
+ status = "disabled";
+ };
+
uart1: serial@01c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
@@ -482,6 +534,16 @@
status = "disabled";
};
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <3>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_APB1_UART2>;
+ status = "disabled";
+ };
+
uart3: serial@01c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
--
git-series 0.8.11
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[PATCH 0/9] ARM: sun5i: Cleanup and reorganisation of the DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-02-06 08:10 +0100
[PATCH 8/9] ARM: sun5i: r8: Merge common controllers into the common DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-02-06 08:10 +0100
Re: [PATCH 8/9] ARM: sun5i: r8: Merge common controllers into the common DTSI Chen-Yu Tsai <wens@csie.org> - 2017-02-06 08:30 +0100
[PATCH 4/9] ARM: sun5i: Add UART2 pin group Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-02-06 08:10 +0100
Re: [PATCH 4/9] ARM: sun5i: Add UART2 pin group Chen-Yu Tsai <wens@csie.org> - 2017-02-06 08:20 +0100
Re: [PATCH 4/9] ARM: sun5i: Add UART2 pin group Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-02-06 21:20 +0100
[PATCH 1/9] ARM: sun5i: A10s: Switch the EMAC pins indices Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-02-06 08:10 +0100
Re: [PATCH 1/9] ARM: sun5i: A10s: Switch the EMAC pins indices Chen-Yu Tsai <wens@csie.org> - 2017-02-06 08:20 +0100
[PATCH 2/9] ARM: sun5i: a10s: switch simple framebuffer indices Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-02-06 08:10 +0100
Re: [PATCH 2/9] ARM: sun5i: a10s: switch simple framebuffer indices Chen-Yu Tsai <wens@csie.org> - 2017-02-06 08:20 +0100
[PATCH 3/9] ARM: sunxi: Rename pwm0_pins to match our usual pattern Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-02-06 08:10 +0100
Re: [PATCH 3/9] ARM: sunxi: Rename pwm0_pins to match our usual pattern Chen-Yu Tsai <wens@csie.org> - 2017-02-06 08:20 +0100
Re: [PATCH 3/9] ARM: sunxi: Rename pwm0_pins to match our usual pattern Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-02-06 21:20 +0100
[PATCH 5/9] ARM: sun5i: Rename UART3 flow control pins Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-02-06 08:10 +0100
Re: [PATCH 5/9] ARM: sun5i: Rename UART3 flow control pins Chen-Yu Tsai <wens@csie.org> - 2017-02-06 08:20 +0100
[PATCH 6/9] ARM: sun5i: a13: Merge common controllers into the common DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-02-06 08:10 +0100
Re: [PATCH 6/9] ARM: sun5i: a13: Merge common controllers into the common DTSI Chen-Yu Tsai <wens@csie.org> - 2017-02-06 08:20 +0100
[PATCH 7/9] ARM: sun5i: a10s: Merge common controllers into the common DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-02-06 08:10 +0100
[PATCH 9/9] ARM: sun5i: gr8: Use common sun5i DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-02-06 08:10 +0100
Re: [PATCH 9/9] ARM: sun5i: gr8: Use common sun5i DTSI Chen-Yu Tsai <wens@csie.org> - 2017-02-06 08:40 +0100
Re: [PATCH 9/9] ARM: sun5i: gr8: Use common sun5i DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-02-06 21:20 +0100
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