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Groups > linux.kernel > #1569723
| From | Thomas Gleixner <tglx@linutronix.de> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [3/8] x86/tsc: Store and check TSC ADJUST MSR |
| Date | 2017-01-30 14:10 +0100 |
| Message-ID | <t5jSy-4oc-33@gated-at.bofh.it> (permalink) |
| References | <sFelr-5AY-13@gated-at.bofh.it> <t4fei-4Q7-13@gated-at.bofh.it> <t5hH4-2Un-9@gated-at.bofh.it> <t5j6a-3SD-23@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Mon, 30 Jan 2017, Henning Schild wrote: > On Mon, 30 Jan 2017 11:20:25 +0100 > Thomas Gleixner <tglx@linutronix.de> wrote: > > There is nothing you can ever be sure about, but I doubt that the > > ADJUST MSR is going to vanish. > > That sounds very much like i expected. But assuming the MSR has come to > stay, the problem should be solved for recent kernels and Intel-CPUs. > > The AMD-Manual from 12/16 does not mention that MSR. I do not have > access to an AMD machine. But i can only assume that bigger machines > also suffer from async TSCs and basically all fall back to HPET. Borislav?
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Re: [3/8] x86/tsc: Store and check TSC ADJUST MSR Henning Schild <henning.schild@siemens.com> - 2017-01-27 15:00 +0100
Re: [3/8] x86/tsc: Store and check TSC ADJUST MSR Thomas Gleixner <tglx@linutronix.de> - 2017-01-30 11:50 +0100
Re: [3/8] x86/tsc: Store and check TSC ADJUST MSR Henning Schild <henning.schild@siemens.com> - 2017-01-30 13:20 +0100
Re: [3/8] x86/tsc: Store and check TSC ADJUST MSR Thomas Gleixner <tglx@linutronix.de> - 2017-01-30 14:10 +0100
Re: [3/8] x86/tsc: Store and check TSC ADJUST MSR Borislav Petkov <bp@alien8.de> - 2017-01-30 17:00 +0100
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