Re: [3/8] x86/tsc: Store and check TSC ADJUST MSR

From	Thomas Gleixner <tglx@linutronix.de>
Newsgroups	linux.kernel
Subject	Re: [3/8] x86/tsc: Store and check TSC ADJUST MSR
Date	2017-01-30 11:50 +0100
Message-ID	<t5hH4-2Un-9@gated-at.bofh.it> (permalink)
References	<sFelr-5AY-13@gated-at.bofh.it> <t4fei-4Q7-13@gated-at.bofh.it>
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Henning,

On Fri, 27 Jan 2017, Henning Schild wrote:
> 
> did you by any chance look into TSC synchronization by adjusting the
> absolute value (MSR_IA32_TSC) as well? As far as i have seen Linux did
> that a long time ago and eventually it was stopped because it caused more
> harm than good.

I was involved in both developing the TSC sync patches and ripping them out
again.

The problem with writing TSC directly is that you really _CANNOT_ reliably
handle run-time differences and SMI/NMI induced deltas. With the adjust MRS
it's a halfways sane thing to do, except for the brokeness of that botch
job vs. the TSC deadline timer.

> The ADJUST MSR offers an easy way to synchronize, still taking care of
> all the special cases resulted in an 8-patch series. Synching without
> that using the absolute value is likely much harder, but that series
> might be a good foundation.

I'm not even thinking about bringing the pure TSC based sync back.

> The big question is whether we can rely on all future CPUs to 
> support that MSR. Do "new MSRs" disappear again at some point? If we
> can not rely on the ADJUST MSR, now might be a good time to revisit the
> idea of synching the absolute values.

There is nothing you can ever be sure about, but I doubt that the ADJUST
MSR is going to vanish.

> I remember having read somewhere that this series might get backported
> to longterm kernels, what is the status on that?

No idea.

Thanks,

	tglx

Thread

Re: [3/8] x86/tsc: Store and check TSC ADJUST MSR Henning Schild <henning.schild@siemens.com> - 2017-01-27 15:00 +0100
  Re: [3/8] x86/tsc: Store and check TSC ADJUST MSR Thomas Gleixner <tglx@linutronix.de> - 2017-01-30 11:50 +0100
    Re: [3/8] x86/tsc: Store and check TSC ADJUST MSR Henning Schild <henning.schild@siemens.com> - 2017-01-30 13:20 +0100
      Re: [3/8] x86/tsc: Store and check TSC ADJUST MSR Thomas Gleixner <tglx@linutronix.de> - 2017-01-30 14:10 +0100
        Re: [3/8] x86/tsc: Store and check TSC ADJUST MSR Borislav Petkov <bp@alien8.de> - 2017-01-30 17:00 +0100

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