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Groups > linux.kernel > #1339687
| From | Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v2 04/15] dmaengine: dw: set src and dst master select according to xfer direction |
| Date | 2016-02-22 17:10 +0100 |
| Message-ID | <r51dF-8d4-39@gated-at.bofh.it> (permalink) |
| References | <r51dD-8d4-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
From: Mans Rullgard <mans@mansr.com> On some architectures the DMA controller can have two masters connected to different buses and thus access to memory is possible only through one and to peripheral through the other. This patch changes the src and dst master setting to match the direction of the transfer. Signed-off-by: Mans Rullgard <mans@mansr.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> --- drivers/dma/dw/core.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index 2573b04..67e8618 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -45,13 +45,17 @@ DW_DMA_MSIZE_16; \ u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ DW_DMA_MSIZE_16; \ + u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ? \ + _dwc->p_master : _dwc->m_master; \ + u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ? \ + _dwc->p_master : _dwc->m_master; \ \ (DWC_CTLL_DST_MSIZE(_dmsize) \ | DWC_CTLL_SRC_MSIZE(_smsize) \ | DWC_CTLL_LLP_D_EN \ | DWC_CTLL_LLP_S_EN \ - | DWC_CTLL_DMS(_dwc->p_master) \ - | DWC_CTLL_SMS(_dwc->m_master)); \ + | DWC_CTLL_DMS(_dms) \ + | DWC_CTLL_SMS(_sms)); \ }) /* -- 2.7.0
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[PATCH v2 00/15] Fixes / cleanups in dw_dmac (affects on few subsystems) Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100 [PATCH v2 10/15] dmaengine: dw: pass platform data via struct dw_dma_chip Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100 [PATCH v2 14/15] dmaengine: dw: move residue to a descriptor Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100 [PATCH v2 07/15] dmaengine: dw: revisit data_width property Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100 [PATCH v2 09/15] dmaengine: dw: keep entire platform data in struct dw_dma Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100 [PATCH v2 01/15] dmaengine: dw: fix byte order of hw descriptor fields Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100 [PATCH v2 11/15] dmaengine: dw: platform: use field-by-field initialization Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100 [PATCH v2 08/15] dmaengine: dw: define counter variables as unsigned int Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100 [PATCH v2 15/15] dmaengine: dw: set cdesc to NULL when free cyclic transfers Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100 [PATCH v2 02/15] dmaengine: dw: clear LLP_[SD]_EN bits in last descriptor of a chain Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100 [PATCH v2 13/15] dmaengine: dw: move dwc->initialized to dwc->flags Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100 [PATCH v2 04/15] dmaengine: dw: set src and dst master select according to xfer direction Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100 [PATCH v2 12/15] dmaengine: dw: move dwc->paused to dwc->flags Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100 [PATCH v2 03/15] dmaengine: dw: rename masters to reflect actual topology Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100 [PATCH v2 06/15] dmaengine: dw: substitute dma_read_byaddr by dma_readl_native Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100 [PATCH v2 05/15] dmaengine: dw: set LMS field in descriptors Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2016-02-22 17:10 +0100
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