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Groups > comp.lang.c++ > #70724
| From | "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> |
|---|---|
| Newsgroups | comp.lang.c++ |
| Subject | Re: What cache-archtectures ... |
| Date | 2019-12-27 23:59 -0800 |
| Organization | Aioe.org NNTP Server |
| Message-ID | <qu7204$pge$3@gioia.aioe.org> (permalink) |
| References | (6 earlier) <qtu0li$mfk$2@gioia.aioe.org> <qtue42$isg$1@news.albasani.net> <qu71jb$pge$1@gioia.aioe.org> <qu71n7$34f$1@news.albasani.net> <qu71u4$pge$2@gioia.aioe.org> |
On 12/27/2019 11:57 PM, Chris M. Thomasson wrote: > On 12/27/2019 11:54 PM, Bonita Montero wrote: >>>>>> Not true. The L1-cache of NetBurst-CPUs had 64 byte lines and the >>>>>> L2-cache 128 byte lines with partitial invalidation of the lower >>>>>> or upper half through the L1-cache. >>>>>> What you say might have been true for Net-Burst based dual-socket >>>>>> Xeons. >> >>>>> https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf >>>>> Section 3.7.3, Hardware Prefetching for Second-Level Cache. >> >>>> Alignment of prefetches is a totally different topic. >> >>> Imvvho, it can present an insight into deeper levels of the cache >>> architecture. >> >> This has nothing to do with false or true sharing if the higher level >> cache with a larger line-size is shared. > > It did with earlier models. The split 128... Best to keep things padded and properly aligned on boundaries. The two halfs are interesting.
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What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-18 16:07 +0100
Re: What cache-archtectures ... Vir Campestris <vir.campestris@invalid.invalid> - 2019-12-20 21:20 +0000
Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-20 14:04 -0800
Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-21 08:18 +0100
Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-22 17:24 -0800
Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-22 17:35 -0800
Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-24 13:18 +0100
Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-24 13:39 -0800
Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-24 13:41 -0800
Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-25 02:30 +0100
Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-27 23:52 -0800
Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-28 08:54 +0100
Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-27 23:57 -0800
Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-27 23:59 -0800
Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-28 09:53 +0100
Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-28 15:56 -0800
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