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Re: What cache-archtectures ...

From "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com>
Newsgroups comp.lang.c++
Subject Re: What cache-archtectures ...
Date 2019-12-27 23:52 -0800
Organization Aioe.org NNTP Server
Message-ID <qu71jb$pge$1@gioia.aioe.org> (permalink)
References (3 earlier) <qtkh0t$mhr$1@news.albasani.net> <qtp50l$khv$1@gioia.aioe.org> <qtsvls$jdt$1@news.albasani.net> <qtu0li$mfk$2@gioia.aioe.org> <qtue42$isg$1@news.albasani.net>

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On 12/24/2019 5:30 PM, Bonita Montero wrote:
>>> Not true. The L1-cache of NetBurst-CPUs had 64 byte lines and the
>>> L2-cache 128 byte lines with partitial invalidation of the lower
>>> or upper half through the L1-cache.
>>> What you say might have been true for Net-Burst based dual-socket
>>> Xeons.
> 
>> https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf 
>> Section 3.7.3, Hardware Prefetching for Second-Level Cache.
> 
> Alignment of prefetches is a totally different topic.

Imvvho, it can present an insight into deeper levels of the cache 
architecture.

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Thread

What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-18 16:07 +0100
  Re: What cache-archtectures ... Vir Campestris <vir.campestris@invalid.invalid> - 2019-12-20 21:20 +0000
    Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-20 14:04 -0800
      Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-21 08:18 +0100
        Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-22 17:24 -0800
          Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-22 17:35 -0800
          Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-24 13:18 +0100
            Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-24 13:39 -0800
            Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-24 13:41 -0800
              Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-25 02:30 +0100
                Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-27 23:52 -0800
                Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-28 08:54 +0100
                Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-27 23:57 -0800
                Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-27 23:59 -0800
                Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-28 09:53 +0100
                Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-28 15:56 -0800

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