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Re: What cache-archtectures ...

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On 12/20/2019 11:18 PM, Bonita Montero wrote:
>> Yeah. Was thinking that std::hardware_destructive_interference_size 
>> can be L1, and std::hardware_constructive_interference_size different 
>> can be L2. However, this is completely up to the implementation.
> 
> If L2 has a larger cacheline-size than L1 and L2 is shared,
> then both values should be at least >= the L2 cacheline-size.
> 
>> Iirc, back on early hyperthreading 128-byte would be split into two 
>> 64-byte halves. Iirc, two adjacent 64-bit cache lines can interfere.
>> https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf 
>> They recommend to pad and align things on 128-byte boundaries. The two 
>> 64-byte halves can contend. Section 3.7.3, Hardware Prefetching for 
>> Second-Level Cache.
> 
> 
> There were multicore NetBurst-CPUs, not even NetBurst-based Xeons.
> So there wasn't any opportunity for false sharing.
>
Iirc, back when hyperthreading first came out, there was/is still an 
issue, with two concurrent threads heavily working on their respective 
contiguous 64-byte structures. They can interfere with one another wrt 
using lock'ed rmw. Therefore, its is recommended to align _and_ pad 
things on a 128-byte boundary. Something like the following structures, 
just some pseudo-code:
_____________________
struct cache_buf
{
     char buf[128];
};

struct cache_half
{
     char buf[64];
};

struct cache_line
{
     cache_half low;
     cache_half high;
};

union cache_line_buf
{
     cache_line line;
     cache_buf buf;
};
_____________________

a cache_line_buf needs to be aligned in memory on a sizeof(cache_buf) 
boundary. Its already padded.

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What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-18 16:07 +0100
  Re: What cache-archtectures ... Vir Campestris <vir.campestris@invalid.invalid> - 2019-12-20 21:20 +0000
    Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-20 14:04 -0800
      Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-21 08:18 +0100
        Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-22 17:24 -0800
          Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-22 17:35 -0800
          Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-24 13:18 +0100
            Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-24 13:39 -0800
            Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-24 13:41 -0800
              Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-25 02:30 +0100
                Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-27 23:52 -0800
                Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-28 08:54 +0100
                Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-27 23:57 -0800
                Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-27 23:59 -0800
                Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-28 09:53 +0100
                Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-28 15:56 -0800

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